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fixed typo

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This commit is contained in:
Blaise Tine
2020-12-09 13:03:22 -08:00
parent fe07ca9aee
commit 3e9abb978b
2 changed files with 9 additions and 5 deletions
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2
hw/rtl/VX_instr_demux.v
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@@ -36,7 +36,7 @@ module VX_instr_demux (
VX_skid_buffer #( VX_skid_buffer #(
.DATAW (`NW_BITS + `NUM_THREADS + 32 + 32 + `ALU_BR_BITS + 1 + 32 + 1 + 1 + `NR_BITS + 1 + `NT_BITS + (2 * `NUM_THREADS * 32)), .DATAW (`NW_BITS + `NUM_THREADS + 32 + 32 + `ALU_BR_BITS + 1 + 32 + 1 + 1 + `NR_BITS + 1 + `NT_BITS + (2 * `NUM_THREADS * 32)),
.REGISTER (1) // ALU has no back pressure, use a simple register .NOBACKPRESSURE (1) // ALU has no back pressure
) alu_buffer ( ) alu_buffer (
.clk (clk), .clk (clk),
.reset (reset), .reset (reset),

12
hw/rtl/libs/VX_skid_buffer.v
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@@ -1,9 +1,9 @@
`include "VX_platform.vh" `include "VX_platform.vh"
module VX_skid_buffer #( module VX_skid_buffer #(
parameter DATAW = 1, parameter DATAW = 1,
parameter PASSTHRU = 0, parameter PASSTHRU = 0,
parameter REGISTER = 0 parameter NOBACKPRESSURE = 0
) ( ) (
input wire clk, input wire clk,
input wire reset, input wire reset,
@@ -26,7 +26,11 @@ module VX_skid_buffer #(
assign data_out = data_in; assign data_out = data_in;
assign ready_in = ready_out; assign ready_in = ready_out;
end if (REGISTER) begin end else if (NOBACKPRESSURE) begin
always @(posedge clk) begin
assert(ready_out) else $error("ready_out should always be asserted");
end
wire stall = valid_out && ~ready_out; wire stall = valid_out && ~ready_out;