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OPAE rtl fixes

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This commit is contained in:
Blaise Tine
2020-05-08 13:16:44 -07:00
parent c2e9240b7d
commit 359601cfd3
4 changed files with 11 additions and 10 deletions
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7
hw/rtl/cache/VX_cache_dram_req_arb.v vendored
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@@ -100,7 +100,9 @@ module VX_cache_dram_req_arb #(
wire dfqq_pop = !dwb_valid && dfqq_req && dram_req_ready; // If no dwb, and dfqq has valids, then pop
wire dfqq_push = (| per_bank_dram_fill_req_valid);
VX_cache_dfq_queue cache_dfq_queue(
VX_cache_dfq_queue #(
) cache_dfq_queue (
.clk (clk),
.reset (reset),
.dfqq_push (dfqq_push),
@@ -128,9 +130,10 @@ module VX_cache_dram_req_arb #(
assign per_bank_dram_wb_queue_pop = dram_req_ready ? (use_wb_valid & ((1 << dwb_bank))) : 0;
wire dram_req_valid = dwb_valid || dfqq_req || pref_pop;
assign dram_req_read = ((dfqq_req && !dwb_valid) || pref_pop) && dram_req_valid;
assign dram_req_write = dwb_valid && dram_req_valid;
assign dram_req_addr = dwb_valid ? per_bank_dram_wb_req_addr[dwb_bank] : (dfqq_req ? dfqq_req_addr : pref_addr);
assign {dram_req_data} = dwb_valid ? {per_bank_dram_wb_req_data[dwb_bank] }: 0;
assign {dram_req_data} = dwb_valid ? per_bank_dram_wb_req_data[dwb_bank] : 0;
endmodule