From 359601cfd3f5d1233fa824c1895b1e53d1a1938c Mon Sep 17 00:00:00 2001 From: Blaise Tine Date: Fri, 8 May 2020 13:16:44 -0700 Subject: [PATCH] OPAE rtl fixes --- hw/rtl/VX_front_end.v | 4 +--- hw/rtl/VX_icache_stage.v | 2 +- hw/rtl/cache/VX_cache_dfq_queue.v | 8 ++++---- hw/rtl/cache/VX_cache_dram_req_arb.v | 7 +++++-- 4 files changed, 11 insertions(+), 10 deletions(-) diff --git a/hw/rtl/VX_front_end.v b/hw/rtl/VX_front_end.v index 7e31e2c0..1cc0c2e9 100644 --- a/hw/rtl/VX_front_end.v +++ b/hw/rtl/VX_front_end.v @@ -50,12 +50,10 @@ module VX_front_end ( .fe_inst_meta_fi (fe_inst_meta_fi) ); - wire freeze_fi_reg = total_freeze || icache_stage_delay; - VX_f_d_reg f_i_reg ( .clk (clk), .reset (reset), - .freeze (freeze_fi_reg), + .freeze (icache_stage_delay), .fe_inst_meta_fd (fe_inst_meta_fi), .fd_inst_meta_de (fe_inst_meta_fi2) ); diff --git a/hw/rtl/VX_icache_stage.v b/hw/rtl/VX_icache_stage.v index edd197e4..e1c2f764 100644 --- a/hw/rtl/VX_icache_stage.v +++ b/hw/rtl/VX_icache_stage.v @@ -24,7 +24,7 @@ module VX_icache_stage ( `DEBUG_END // Icache Request - assign icache_req_if.core_req_valid = valid_inst && !total_freeze; + assign icache_req_if.core_req_valid = valid_inst; assign icache_req_if.core_req_addr = fe_inst_meta_fi.inst_pc; assign icache_req_if.core_req_data = 'z; assign icache_req_if.core_req_read = `BYTE_EN_LW; diff --git a/hw/rtl/cache/VX_cache_dfq_queue.v b/hw/rtl/cache/VX_cache_dfq_queue.v index b651e024..eafb77d6 100644 --- a/hw/rtl/cache/VX_cache_dfq_queue.v +++ b/hw/rtl/cache/VX_cache_dfq_queue.v @@ -2,13 +2,13 @@ module VX_cache_dfq_queue #( // Size of cache in bytes - parameter CACHE_SIZE = 1024, + parameter CACHE_SIZE = 1024, // Size of line inside a bank in bytes - parameter BANK_LINE_SIZE = 16, + parameter BANK_LINE_SIZE = 16, // Number of banks {1, 2, 4, 8,...} parameter NUM_BANKS = 8, // Size of a word in bytes - parameter WORD_SIZE = 4, + parameter WORD_SIZE = 4, // Number of Word requests per cycle {1, 2, 4, 8, ...} parameter NUM_REQUESTS = 2, // Number of cycles to complete stage 1 (read from memory) @@ -35,7 +35,7 @@ module VX_cache_dfq_queue #( parameter LLVQ_SIZE = 16, // Fill Invalidator Size {Fill invalidator must be active} - parameter FILL_INVALIDAOR_SIZE = 16 + parameter FILL_INVALIDAOR_SIZE = 16 ) ( input wire clk, input wire reset, diff --git a/hw/rtl/cache/VX_cache_dram_req_arb.v b/hw/rtl/cache/VX_cache_dram_req_arb.v index fa895762..8f242b1c 100644 --- a/hw/rtl/cache/VX_cache_dram_req_arb.v +++ b/hw/rtl/cache/VX_cache_dram_req_arb.v @@ -100,7 +100,9 @@ module VX_cache_dram_req_arb #( wire dfqq_pop = !dwb_valid && dfqq_req && dram_req_ready; // If no dwb, and dfqq has valids, then pop wire dfqq_push = (| per_bank_dram_fill_req_valid); - VX_cache_dfq_queue cache_dfq_queue( + VX_cache_dfq_queue #( + + ) cache_dfq_queue ( .clk (clk), .reset (reset), .dfqq_push (dfqq_push), @@ -128,9 +130,10 @@ module VX_cache_dram_req_arb #( assign per_bank_dram_wb_queue_pop = dram_req_ready ? (use_wb_valid & ((1 << dwb_bank))) : 0; wire dram_req_valid = dwb_valid || dfqq_req || pref_pop; + assign dram_req_read = ((dfqq_req && !dwb_valid) || pref_pop) && dram_req_valid; assign dram_req_write = dwb_valid && dram_req_valid; assign dram_req_addr = dwb_valid ? per_bank_dram_wb_req_addr[dwb_bank] : (dfqq_req ? dfqq_req_addr : pref_addr); - assign {dram_req_data} = dwb_valid ? {per_bank_dram_wb_req_data[dwb_bank] }: 0; + assign {dram_req_data} = dwb_valid ? per_bank_dram_wb_req_data[dwb_bank] : 0; endmodule \ No newline at end of file