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fixed register file initialization to zero synthesis inference

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Blaise Tine
2020-12-10 00:27:56 -08:00
parent 3e9abb978b
commit 29cd2f5dff
10 changed files with 171 additions and 130 deletions
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2
driver/opae/Makefile
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@@ -85,7 +85,7 @@ vlsim-hw: $(SCOPE_H)
fpga: $(SRCS) $(SCOPE_H)
$(CXX) $(CXXFLAGS) -DUSE_FPGA $^ $(LDFLAGS) $(FPGA_LIBS) -o $(PROJECT)
asesim: $(SRCS) $(ASE_DIR)
asesim: $(SRCS) $(ASE_DIR) $(SCOPE_H)
$(CXX) $(CXXFLAGS) -DUSE_ASE $(SRCS) $(LDFLAGS) $(ASE_LIBS) -o $(PROJECT_ASE)
vlsim: $(SRCS) vlsim-hw