cache area optimization by disabling BRAM read-during-write bypassing for tag/data stores

2021-08-26 12:27:38 -07:00
parent 74a45e2772
commit 26e94dde44
5 changed files with 23 additions and 10 deletions
--- a/hw/rtl/cache/VX_shared_mem.v
+++ b/hw/rtl/cache/VX_shared_mem.v
@@ -171,9 +171,10 @@ module VX_shared_mem #(
                 && creq_out_fire;

        VX_sp_ram #(
-            .DATAW   (`WORD_WIDTH),
-            .SIZE    (`LINES_PER_BANK),
-            .BYTEENW (WORD_SIZE)
+            .DATAW      (`WORD_WIDTH),
+            .SIZE       (`LINES_PER_BANK),
+            .BYTEENW    (WORD_SIZE),
+            .NO_RWCHECK (1)
        ) data_store (
            .clk   (clk),
            .addr  (per_bank_core_req_addr[i]),