From 26e94dde44119c678bf5ca1becae682993d89f3a Mon Sep 17 00:00:00 2001
From: Blaise Tine <tinebp@yahoo.com>
Date: Thu, 26 Aug 2021 12:27:38 -0700
Subject: [PATCH] cache area optimization by disabling BRAM  read-during-write
 bypassing for tag/data stores

---
 hw/rtl/cache/VX_bank.v        | 3 +++
 hw/rtl/cache/VX_data_access.v | 7 ++++---
 hw/rtl/cache/VX_shared_mem.v  | 7 ++++---
 hw/rtl/cache/VX_tag_access.v  | 9 +++++----
 hw/syn/opae/fpga_prog.sh      | 7 +++++++
 5 files changed, 23 insertions(+), 10 deletions(-)
 create mode 100755 hw/syn/opae/fpga_prog.sh

diff --git a/hw/rtl/cache/VX_bank.v b/hw/rtl/cache/VX_bank.v
index e1b3a270..6dda9a93 100644
--- a/hw/rtl/cache/VX_bank.v
+++ b/hw/rtl/cache/VX_bank.v
@@ -161,6 +161,8 @@ module VX_bank #(
     wire mreq_alm_full;
 
     wire creq_fire = creq_valid && creq_ready;
+
+    wire fill_in_st0 = valid_st0 && is_fill_st0;
     
     // determine which queue to pop next in priority order 
     wire mshr_grant  = 1;
@@ -172,6 +174,7 @@ module VX_bank #(
     wire creq_grant  = !mshr_enable && !mrsq_enable && !flush_enable;
     
     wire mshr_ready = mshr_grant
+                   && !fill_in_st0      // prevent tag read-during-write with fill
                    && !crsq_stall;      // ensure core response ready
 
     assign mem_rsp_ready = mrsq_grant
diff --git a/hw/rtl/cache/VX_data_access.v b/hw/rtl/cache/VX_data_access.v
index f3700e5f..64541f7b 100644
--- a/hw/rtl/cache/VX_data_access.v
+++ b/hw/rtl/cache/VX_data_access.v
@@ -63,9 +63,10 @@ module VX_data_access #(
     end
 
     VX_sp_ram #(
-        .DATAW   (CACHE_LINE_SIZE * 8),
-        .SIZE    (`LINES_PER_BANK),
-        .BYTEENW (BYTEENW)
+        .DATAW      (CACHE_LINE_SIZE * 8),
+        .SIZE       (`LINES_PER_BANK),
+        .BYTEENW    (BYTEENW),
+        .NO_RWCHECK (1)
     ) data_store (
         .clk   (clk),        
         .addr  (line_addr),
diff --git a/hw/rtl/cache/VX_shared_mem.v b/hw/rtl/cache/VX_shared_mem.v
index 71a49b3c..00edeab0 100644
--- a/hw/rtl/cache/VX_shared_mem.v
+++ b/hw/rtl/cache/VX_shared_mem.v
@@ -171,9 +171,10 @@ module VX_shared_mem #(
                  && creq_out_fire;
 
         VX_sp_ram #(
-            .DATAW   (`WORD_WIDTH),
-            .SIZE    (`LINES_PER_BANK),
-            .BYTEENW (WORD_SIZE)
+            .DATAW      (`WORD_WIDTH),
+            .SIZE       (`LINES_PER_BANK),
+            .BYTEENW    (WORD_SIZE),
+            .NO_RWCHECK (1)
         ) data_store (
             .clk   (clk),
             .addr  (per_bank_core_req_addr[i]),
diff --git a/hw/rtl/cache/VX_tag_access.v b/hw/rtl/cache/VX_tag_access.v
index 0c51de01..708220ae 100644
--- a/hw/rtl/cache/VX_tag_access.v
+++ b/hw/rtl/cache/VX_tag_access.v
@@ -46,10 +46,11 @@ module VX_tag_access #(
     wire [`LINE_SELECT_BITS-1:0] line_addr = addr [`LINE_SELECT_BITS-1:0];
 
     VX_sp_ram #(
-        .DATAW(`TAG_SELECT_BITS + 1),
-        .SIZE(`LINES_PER_BANK),
-        .INIT_ENABLE(1),
-        .INIT_VALUE(0)
+        .DATAW       (`TAG_SELECT_BITS + 1),
+        .SIZE        (`LINES_PER_BANK),
+        .INIT_ENABLE (1),
+        .INIT_VALUE  (0),
+        .NO_RWCHECK  (1)
     ) tag_store (
         .clk(  clk),                 
         .addr  (line_addr),   
diff --git a/hw/syn/opae/fpga_prog.sh b/hw/syn/opae/fpga_prog.sh
new file mode 100755
index 00000000..4fc9db22
--- /dev/null
+++ b/hw/syn/opae/fpga_prog.sh
@@ -0,0 +1,7 @@
+#!/bin/bash
+
+# FPGA programming
+# first argument is the bitstream
+
+echo "fpgaconf --bus 0xaf $1"
+fpgaconf --bus 0xaf $1
\ No newline at end of file