cache area optimization by disabling BRAM read-during-write bypassing for tag/data stores

2021-08-26 12:27:38 -07:00
parent 74a45e2772
commit 26e94dde44
5 changed files with 23 additions and 10 deletions
--- a/hw/rtl/cache/VX_data_access.v
+++ b/hw/rtl/cache/VX_data_access.v
@@ -63,9 +63,10 @@ module VX_data_access #(
    end

    VX_sp_ram #(
-        .DATAW   (CACHE_LINE_SIZE * 8),
-        .SIZE    (`LINES_PER_BANK),
-        .BYTEENW (BYTEENW)
+        .DATAW      (CACHE_LINE_SIZE * 8),
+        .SIZE       (`LINES_PER_BANK),
+        .BYTEENW    (BYTEENW),
+        .NO_RWCHECK (1)
    ) data_store (
        .clk   (clk),        
        .addr  (line_addr),