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Merge branch 'master' of https://github.gatech.edu/casl/Vortex

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This commit is contained in:
Blaise Tine
2020-06-30 00:08:44 -07:00
parent 2de61b5982 d7ef5f0bd7
commit 1f5c4bf617
9 changed files with 167 additions and 11 deletions
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27
hw/rtl/VX_back_end.v
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@@ -9,6 +9,10 @@ module VX_back_end #(
input wire clk,
input wire reset,
// IO CSR
VX_csr_req_if io_csr_req,
VX_wb_if io_csr_rsp,
input wire schedule_delay,
VX_cache_core_req_if dcache_req_if,
@@ -31,6 +35,7 @@ module VX_back_end #(
wire no_slot_mem;
wire no_slot_exec;
// LSU input + output
VX_lsu_req_if lsu_req_if();
VX_wb_if mem_wb_if();
@@ -99,15 +104,33 @@ module VX_back_end #(
.warp_ctl_if (warp_ctl_if)
);
VX_csr_req_if issued_csr_req();
VX_wb_if csr_pipe_rsp();
VX_csr_arbiter csr_arbiter (
.clk (clk),
.reset (reset),
.csr_pipe_stall(stall_gpr_csr),
.core_csr_req (csr_req_if),
.io_csr_req (io_csr_req),
.issued_csr_req(issued_csr_req),
.csr_pipe_rsp (csr_pipe_rsp),
.csr_wb_if (csr_wb_if),
.csr_io_rsp (io_csr_rsp)
);
VX_csr_pipe #(
.CORE_ID(CORE_ID)
) csr_pipe (
.clk (clk),
.reset (reset),
.no_slot_csr (no_slot_csr),
.csr_req_if (csr_req_if),
.csr_req_if (issued_csr_req),
.writeback_if (writeback_if),
.csr_wb_if (csr_wb_if),
.csr_wb_if (csr_pipe_rsp),
.stall_gpr_csr (stall_gpr_csr)
);

15
hw/rtl/VX_cluster.v
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@@ -174,6 +174,19 @@ module VX_cluster #(
.io_rsp_tag (per_core_io_rsp_tag [i]),
.io_rsp_ready (per_core_io_rsp_ready [i]),
.csr_io_req_valid (1'b0), // Valid CSR IO Request
`UNUSED_PIN(csr_io_req_ready), // Core is ready to accept Request
`UNUSED_PIN(csr_io_req_cid), // CORE_ID of the intended request
`UNUSED_PIN(csr_io_req_addr), // ADDRESS of request
`UNUSED_PIN(csr_io_req_rw), // Read=0, Write=1
`UNUSED_PIN(csr_io_req_data), // Data to write
`UNUSED_PIN(csr_io_rsp_valid), // Core IO Response valid
`UNUSED_PIN(csr_io_rsp_data), // Core IO Response data
.busy (per_core_busy [i]),
.ebreak (per_core_ebreak [i])
);
@@ -537,4 +550,4 @@ module VX_cluster #(
end
endmodule
endmodule

42
hw/rtl/VX_core.v
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@@ -70,12 +70,47 @@ module VX_core #(
input wire [`DCORE_TAG_WIDTH-1:0] io_rsp_tag,
output wire io_rsp_ready,
// IO CSR Request
input wire csr_io_req_valid,
input wire[`NC_BITS-1:0] csr_io_req_cid,
input wire[11:0] csr_io_req_addr,
input wire csr_io_req_rw,
input wire[31:0] csr_io_req_data,
output wire csr_io_req_ready,
// IO CSR Response
output wire csr_io_rsp_valid,
output wire[31:0] csr_io_rsp_data,
// Status
output wire busy,
output wire ebreak
);
// Dcache Interfaces
// IO CSR request
VX_csr_req_if io_csr_req();
wire temp_io_csr_req_valid = csr_io_req_valid & (csr_io_req_cid == CORE_ID[`NC_BITS-1:0]);
assign io_csr_req.valid = {`NUM_THREADS{temp_io_csr_req_valid}};
assign io_csr_req.is_csr = 1'b1;
assign io_csr_req.csr_address = csr_io_req_addr;
assign io_csr_req.alu_op = csr_io_req_rw ? `ALU_CSR_RW : `ALU_CSR_RS;
assign io_csr_req.csr_mask = csr_io_req_rw ? csr_io_req_data : 32'b0;
VX_wb_if io_csr_rsp();
assign csr_io_req_ready = io_csr_rsp.is_io;
assign csr_io_rsp_valid = io_csr_rsp.valid[0];
assign csr_io_rsp_data = io_csr_rsp.data[0];
`IGNORE_WARNINGS_BEGIN
wire [4:0] unused_rd = io_csr_rsp.rd;
wire [1:0] unused_wb = io_csr_rsp.wb;
wire [31:0] unused_curr_PC = io_csr_rsp.curr_PC;
`IGNORE_WARNINGS_END
// Dcache Interfaces
VX_cache_dram_req_if #(
.DRAM_LINE_WIDTH(`DDRAM_LINE_WIDTH),
.DRAM_ADDR_WIDTH(`DDRAM_ADDR_WIDTH),
@@ -178,6 +213,11 @@ module VX_core #(
.clk(clk),
.reset(reset),
// IO CSR
.io_csr_req (io_csr_req),
.io_csr_rsp (io_csr_rsp),
// Dcache core request
.dcache_req_valid (core_dcache_req_if.core_req_valid),
.dcache_req_rw (core_dcache_req_if.core_req_rw),

64
hw/rtl/VX_csr_arbiter.v Normal file
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@@ -0,0 +1,64 @@
`include "VX_define.vh"
module VX_csr_arbiter (
input wire clk,
input wire reset,
input wire csr_pipe_stall,
VX_csr_req_if core_csr_req,
VX_csr_req_if io_csr_req,
VX_csr_req_if issued_csr_req,
VX_wb_if csr_pipe_rsp,
VX_wb_if csr_wb_if,
VX_wb_if csr_io_rsp
);
`UNUSED_VAR (clk)
`UNUSED_VAR (reset)
wire pick_core = (|core_csr_req.valid);
// Which request to pick
assign issued_csr_req.is_io = !pick_core;
// Mux between core and io
assign issued_csr_req.valid = pick_core ? core_csr_req.valid : io_csr_req.valid;
assign issued_csr_req.is_csr = pick_core ? core_csr_req.is_csr : io_csr_req.is_csr;
assign issued_csr_req.alu_op = pick_core ? core_csr_req.alu_op : io_csr_req.alu_op;
assign issued_csr_req.csr_address = pick_core ? core_csr_req.csr_address : io_csr_req.csr_address;
assign issued_csr_req.csr_mask = pick_core ? core_csr_req.csr_mask : io_csr_req.csr_mask;
// Core arguments
assign issued_csr_req.warp_num = core_csr_req.warp_num;
assign issued_csr_req.rd = core_csr_req.rd;
assign issued_csr_req.wb = core_csr_req.wb;
// Core Writeback
assign csr_wb_if.valid = csr_pipe_rsp.valid & {`NUM_THREADS{~csr_pipe_rsp.is_io}};
assign csr_wb_if.data = csr_pipe_rsp.data;
assign csr_wb_if.warp_num = csr_pipe_rsp.warp_num;
assign csr_wb_if.rd = csr_pipe_rsp.rd;
assign csr_wb_if.wb = csr_pipe_rsp.wb;
assign csr_wb_if.curr_PC = csr_pipe_rsp.curr_PC;
assign csr_wb_if.is_io = 1'b0;
// CSR IO WB
assign csr_io_rsp.valid = csr_pipe_rsp.valid & {`NUM_THREADS{csr_pipe_rsp.is_io}};
assign csr_io_rsp.data = csr_pipe_rsp.data;
assign csr_io_rsp.warp_num = csr_pipe_rsp.warp_num;
assign csr_io_rsp.rd = csr_pipe_rsp.rd;
assign csr_io_rsp.wb = csr_pipe_rsp.wb;
assign csr_io_rsp.curr_PC = csr_pipe_rsp.curr_PC;
assign csr_io_rsp.is_io = !(csr_pipe_stall || pick_core);
endmodule

6
hw/rtl/VX_csr_pipe.v
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@@ -55,14 +55,14 @@ module VX_csr_pipe #(
end
VX_generic_register #(
.N(32 + 32 + 12 + 1 + 2 + 5 + (`NW_BITS-1+1) + `NUM_THREADS)
.N(32 + 32 + 12 + 1 + 1 + 2 + 5 + (`NW_BITS-1+1) + `NUM_THREADS)
) csr_reg_s2 (
.clk (clk),
.reset(reset),
.stall(no_slot_csr),
.flush(1'b0),
.in ({csr_req_if.valid, csr_req_if.warp_num, csr_req_if.rd, csr_req_if.wb, csr_req_if.is_csr, csr_req_if.csr_address, csr_read_data , csr_updated_data }),
.out ({valid_s2 , warp_num_s2 , rd_s2 , wb_s2 , is_csr_s2 , csr_address_s2 , csr_read_data_s2, csr_updated_data_s2})
.in ({csr_req_if.valid, csr_req_if.warp_num, csr_req_if.rd, csr_req_if.wb, csr_req_if.is_csr, csr_req_if.csr_address, csr_req_if.is_io, csr_read_data , csr_updated_data }),
.out ({valid_s2 , warp_num_s2 , rd_s2 , wb_s2 , is_csr_s2 , csr_address_s2 , csr_wb_if.is_io , csr_read_data_s2, csr_updated_data_s2})
);
assign csr_wb_if.valid = valid_s2;

6
hw/rtl/VX_gpr_stage.v
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@@ -30,6 +30,9 @@ module VX_gpr_stage (
wire is_jal = bckE_req_if.is_jal;
`DEBUG_END
assign csr_req_if.is_io = 1'b0; // GPR only issues csr requests coming from core
VX_gpr_read_if gpr_read_if();
assign gpr_read_if.rs1 = bckE_req_if.rs1;
assign gpr_read_if.rs2 = bckE_req_if.rs2;
@@ -171,6 +174,7 @@ module VX_gpr_stage (
.out ({csr_req_if.valid , csr_req_if.warp_num , csr_req_if.rd , csr_req_if.wb , csr_req_if.alu_op , csr_req_if.is_csr , csr_req_if.csr_address , csr_req_if.csr_immed , csr_req_if.csr_mask })
);
`else
// 341
@@ -220,4 +224,4 @@ module VX_gpr_stage (
`endif
endmodule : VX_gpr_stage
endmodule : VX_gpr_stage

8
hw/rtl/VX_pipeline.v
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@@ -12,6 +12,10 @@ module VX_pipeline #(
input wire clk,
input wire reset,
// IO CSR
VX_csr_req_if io_csr_req,
VX_wb_if io_csr_rsp,
// Dcache core request
output wire [`NUM_THREADS-1:0] dcache_req_valid,
output wire [`NUM_THREADS-1:0] dcache_req_rw,
@@ -134,6 +138,8 @@ module VX_pipeline #(
.clk (clk),
.reset (reset),
.io_csr_req (io_csr_req),
.io_csr_rsp (io_csr_rsp),
.schedule_delay (schedule_delay),
.warp_ctl_if (warp_ctl_if),
.bckE_req_if (bckE_req_if),
@@ -191,4 +197,4 @@ module VX_pipeline #(
end
`endif
endmodule
endmodule

5
hw/rtl/interfaces/VX_csr_req_if.v
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@@ -15,6 +15,9 @@ interface VX_csr_req_if ();
wire csr_immed;
wire [31:0] csr_mask;
`IGNORE_WARNINGS_BEGIN
wire is_io;
`IGNORE_WARNINGS_END
endinterface
`endif
`endif

5
hw/rtl/interfaces/VX_wb_if.v
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@@ -12,6 +12,9 @@ interface VX_wb_if ();
wire [1:0] wb;
wire [31:0] curr_PC;
`IGNORE_WARNINGS_BEGIN
wire is_io;
`IGNORE_WARNINGS_END
endinterface
`endif
`endif