sgemm_gemmini_dma: Initial activation kernel with gemmini+DMA
Currently does spurrious fmul's in repetition.
This commit is contained in:
Hansung Kim
314
tests/regression/sgemm_gemmini_dma/kernel.activation.cpp
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314
tests/regression/sgemm_gemmini_dma/kernel.activation.cpp
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#include <stdint.h>
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#include <vx_intrinsics.h>
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#include <vx_print.h>
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#include <vx_spawn.h>
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#include "common.h"
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#include "include/gemmini.h"
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#include "gemmini_mmio.h"
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#define TILE_M 64
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#define TILE_N 64
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#define TILE_K 64
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#define SMEM_ADDR_Q0 ((float * const) 0xff000000)
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#define SMEM_ADDR_Q1 ((float * const) 0xff004000)
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#define SMEM_ADDR_Q2 ((float * const) 0xff008000)
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#define SMEM_ADDR_Q3 ((float * const) 0xff00c000)
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#define SPAD_ADDR_Q0 0x0
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#define SPAD_ADDR_Q1 0x200
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#define SPAD_ADDR_Q2 0x400
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#define SPAD_ADDR_Q3 0x600
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#define BOUND_INST 0x800080008ULL
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// #define TILE_M 32
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// #define TILE_N 32
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// #define TILE_K 32
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// #define SMEM_ADDR_Q0 ((float * const) 0xff000000)
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// #define SMEM_ADDR_Q1 ((float * const) 0xff001000)
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// #define SMEM_ADDR_Q2 ((float * const) 0xff002000)
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// #define SMEM_ADDR_Q3 ((float * const) 0xff003000)
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// #define SPAD_ADDR_Q0 0x0
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// #define SPAD_ADDR_Q1 0x80
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// #define SPAD_ADDR_Q2 0x100
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// #define SPAD_ADDR_Q3 0x180
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// #define BOUND_INST 0x400040004ULL
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#define WM 16
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#define WN 8
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#define ELEM_PER_THREAD ((WM * WN) / NUM_THREADS)
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// FIXME: NUM_THREADS and NUM_WARPS hardcoded
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#if ((TILE_M * TILE_N / ELEM_PER_THREAD) > (CORES_PER_CLUSTER * 8 * 8))
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#error "threadblock size too big for cluster"
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#endif
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#define NUM_THREADS_IN_CLUSTER 256 \
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// (NUM_CORES * NUM_WARPS * NUM_THREADS)
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#define rd_cycles_force(x) asm volatile ("csrr %0, mcycle" : "=r" (x))
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#define rd_cycles(x) rd_cycles_force(x)
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#define HW_TID() ({uint32_t gtid; asm volatile ("csrr %0, mhartid" : "=r" (gtid)); gtid;})
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#define PRINTF(...) sprintf(PRINT_BUF, __VA_ARGS__)
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// #define PRINTF(...) vx_printf(__VA_ARGS__)
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#define SWISH(beta, x) ((x) / (1 + exp(-(beta) * (x))))
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//#define POWER
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inline void threadblock_barrier(unsigned int barrier_id, unsigned int count) {
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vx_fence();
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vx_barrier(barrier_id, count);
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}
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void thread_block_matmul_gemmini(kernel_arg_t *__UNIFORM__ arg,
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const uint32_t threadblock_id,
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const uint32_t tid_in_threadblock) {
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asm volatile ("matmul_start_%=:" :: );
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const float * const A = (const float * const) arg->addr_a;
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const float * const B = (const float * const) arg->addr_b;
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float * const C = (float * const) arg->addr_c;
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if (HW_TID() == 0) {
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gemmini_extended_config_ex(WEIGHT_STATIONARY, 0, 0, 1, 0, 0);
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// gemmini_extended_config_ex(dataflow, act & 3, 0, 1, a_transpose, b_transpose);
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PRINTF("start\n");
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}
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vx_fence();
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uint32_t marker0, marker1;
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rd_cycles_force(marker0);
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const uint32_t dim_m = arg->dim_m;
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const uint32_t dim_n = arg->dim_n;
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const uint32_t dim_k = arg->dim_k;
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const uint32_t num_tiles_m = dim_m / TILE_M;
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const uint32_t num_tiles_n = dim_n / TILE_N;
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const uint32_t num_tiles_k = dim_k / TILE_K;
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constexpr uint32_t num_threads_in_cluster = NUM_THREADS_IN_CLUSTER;
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const uint32_t local_c_row = tid_in_threadblock / TILE_N;
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const uint32_t local_c_col = tid_in_threadblock % TILE_N;
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const uint32_t warp_id_in_threadblock = tid_in_threadblock / NUM_THREADS;
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const uint32_t warp_row = warp_id_in_threadblock / (TILE_N / WN);
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const uint32_t warp_col = warp_id_in_threadblock % (TILE_N / WN);
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const uint32_t num_tile_rows_per_tb = num_tiles_m / NUM_CLUSTERS;
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if (HW_TID() == 0) {
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gemmini_extended3_config_ld(dim_k * sizeof(elem_t), MVIN_SCALE_IDENTITY, false, 0);
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gemmini_extended3_config_ld(dim_n * sizeof(elem_t), MVIN_SCALE_IDENTITY, false, 1);
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// gemmini_extended3_config_ld(repeating_bias ? 0 : (stride_D * sizeof_D), D_scale_factor, low_D, 2);
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gemmini_extended_config_st(dim_n * sizeof(elem_t), 0, MVIN_SCALE_IDENTITY);
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// gemmini_extended_config_st(stride_C * sizeof_C, act & 3, scale);
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}
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for (uint32_t tile_i = num_tile_rows_per_tb * threadblock_id;
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tile_i < num_tile_rows_per_tb * (threadblock_id + 1);
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tile_i += 1) {
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for (int tile_j = 0; tile_j < num_tiles_n; tile_j += 1) {
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for (int tile_k = 0; tile_k < num_tiles_k; tile_k += 1) {
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if (HW_TID() == 0) {
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ROCC_INSTRUCTION_RS1_RS2(XCUSTOM_ACC,
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(uint64_t) (A + tile_i * TILE_M * dim_k + tile_k * TILE_K),
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(uint64_t) (B + tile_k * TILE_K * dim_n + tile_j * TILE_N), k_LOOP_WS_CONFIG_ADDRS_AB)
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GEMMINI_CISC_CMD_R((dim_n) << 16 | (dim_k << 8) | 8);
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// DMA move in GMEM->SMEM
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if (tile_k & 1) {
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GEMMINI_CISC_CMD_I(11);
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} else {
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GEMMINI_CISC_CMD_I(10);
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}
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// compute
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if (tile_k == 0) {
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gemmini_fence();
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GEMMINI_CISC_CMD_I(0);
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} else if (tile_k & 1) {
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gemmini_fence();
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GEMMINI_CISC_CMD_I(2);
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} else {
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gemmini_fence();
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GEMMINI_CISC_CMD_I(1);
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}
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}
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}
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// while Gemmini is computing, software-pipeline with activation on the
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// previous (M,N) tile
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if (true || (tid_in_threadblock >= NUM_THREADS)) {
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// activation code currently assumes that the column-width of a warp
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// tile exactly matches SIMD width
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static_assert(WN == NUM_THREADS);
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float elem[ELEM_PER_THREAD];
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const uint32_t col_in_warptile = tid_in_threadblock % WN;
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// const uint32_t row_in_warptile = elem_i; // FIXME: doesn't work with WN != NUM_THREADS
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const uint32_t row_in_warptile = 0;
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const uint32_t C_row = (tile_i * TILE_M) + (warp_row * WM) + row_in_warptile;
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const uint32_t C_col = (tile_j * TILE_N) + (warp_col * WN) + col_in_warptile;
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const float *global_C = C + dim_n * C_row + C_col;
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// read in elements from GMEM to RF
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asm volatile("flw f0, (%0)" :: "r"(global_C));
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global_C += dim_n;
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asm volatile("flw f1, (%0)" :: "r"(global_C));
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global_C += dim_n;
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asm volatile("flw f2, (%0)" :: "r"(global_C));
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global_C += dim_n;
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asm volatile("flw f3, (%0)" :: "r"(global_C));
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global_C += dim_n;
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asm volatile("flw f4, (%0)" :: "r"(global_C));
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global_C += dim_n;
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asm volatile("flw f5, (%0)" :: "r"(global_C));
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global_C += dim_n;
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asm volatile("flw f6, (%0)" :: "r"(global_C));
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global_C += dim_n;
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asm volatile("flw f7, (%0)" :: "r"(global_C));
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global_C += dim_n;
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asm volatile("flw f8, (%0)" :: "r"(global_C));
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global_C += dim_n;
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asm volatile("flw f9, (%0)" :: "r"(global_C));
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global_C += dim_n;
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asm volatile("flw f10, (%0)" :: "r"(global_C));
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global_C += dim_n;
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asm volatile("flw f11, (%0)" :: "r"(global_C));
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global_C += dim_n;
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asm volatile("flw f12, (%0)" :: "r"(global_C));
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global_C += dim_n;
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asm volatile("flw f13, (%0)" :: "r"(global_C));
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global_C += dim_n;
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asm volatile("flw f14, (%0)" :: "r"(global_C));
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global_C += dim_n;
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asm volatile("flw f15, (%0)" :: "r"(global_C));
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global_C += dim_n;
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asm volatile("fcvt.s.w f16, %0, rtz" :: "r"(2));
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// do elem-wise compute in RF
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#pragma GCC unroll
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for (uint32_t count = 0; count < 8; count++) {
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asm volatile("fmul.s f0, f0, f16");
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asm volatile("fmul.s f1, f1, f16");
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asm volatile("fmul.s f2, f2, f16");
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asm volatile("fmul.s f3, f3, f16");
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asm volatile("fmul.s f4, f4, f16");
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asm volatile("fmul.s f5, f5, f16");
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asm volatile("fmul.s f6, f6, f16");
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asm volatile("fmul.s f7, f7, f16");
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asm volatile("fmul.s f8, f8, f16");
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asm volatile("fmul.s f9, f9, f16");
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asm volatile("fmul.s f10, f10, f16");
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asm volatile("fmul.s f11, f11, f16");
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asm volatile("fmul.s f12, f12, f16");
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asm volatile("fmul.s f13, f13, f16");
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asm volatile("fmul.s f14, f14, f16");
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asm volatile("fmul.s f15, f15, f16");
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}
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// move back from RF to gmem
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global_C = C + dim_n * C_row + C_col;
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asm volatile("fsw f0, (%0)" :: "r"(global_C));
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global_C += dim_n;
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asm volatile("fsw f1, (%0)" :: "r"(global_C));
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global_C += dim_n;
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asm volatile("fsw f2, (%0)" :: "r"(global_C));
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global_C += dim_n;
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asm volatile("fsw f3, (%0)" :: "r"(global_C));
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global_C += dim_n;
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asm volatile("fsw f4, (%0)" :: "r"(global_C));
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global_C += dim_n;
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asm volatile("fsw f5, (%0)" :: "r"(global_C));
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global_C += dim_n;
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asm volatile("fsw f6, (%0)" :: "r"(global_C));
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global_C += dim_n;
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asm volatile("fsw f7, (%0)" :: "r"(global_C));
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global_C += dim_n;
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asm volatile("fsw f8, (%0)" :: "r"(global_C));
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global_C += dim_n;
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asm volatile("fsw f9, (%0)" :: "r"(global_C));
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global_C += dim_n;
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asm volatile("fsw f10, (%0)" :: "r"(global_C));
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global_C += dim_n;
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asm volatile("fsw f11, (%0)" :: "r"(global_C));
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global_C += dim_n;
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asm volatile("fsw f12, (%0)" :: "r"(global_C));
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global_C += dim_n;
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asm volatile("fsw f13, (%0)" :: "r"(global_C));
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global_C += dim_n;
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asm volatile("fsw f14, (%0)" :: "r"(global_C));
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global_C += dim_n;
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asm volatile("fsw f15, (%0)" :: "r"(global_C));
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global_C += dim_n;
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}
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if (HW_TID() == 0) {
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// fence the tile computation after activation; depending on the
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// duration of activation, this can be no-op
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gemmini_fence();
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gemmini_fence();
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gemmini_fence();
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gemmini_fence();
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// mvout to scratchpad for activation
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GEMMINI_CISC_CMD_I(9);
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gemmini_fence();
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}
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threadblock_barrier(/*barrier_id=*/0, /*count=*/NUM_WARPS);
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// move out to dram
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if (HW_TID() == 0) {
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float * const dram_c_tile_start = C + tile_i * TILE_M * dim_n + tile_j * TILE_N;
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ROCC_INSTRUCTION_RS1_RS2(XCUSTOM_ACC, 0, BOUND_INST, k_LOOP_WS_CONFIG_BOUNDS)
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ROCC_INSTRUCTION_RS1_RS2(XCUSTOM_ACC, 0, (uint64_t) dram_c_tile_start, k_LOOP_WS_CONFIG_ADDRS_DC)
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ROCC_INSTRUCTION_RS1_RS2(XCUSTOM_ACC, 0, dim_n, k_LOOP_WS_CONFIG_STRIDES_DC)
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ROCC_INSTRUCTION_RS1_RS2(XCUSTOM_ACC, 0,
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loop_matmul_skips(1, 1, 1, 1, 0 /*store C*/),
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k_LOOP_WS)
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}
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}
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}
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// last thread block complete
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if (threadblock_id == NUM_CLUSTERS - 1) {
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threadblock_barrier(/*barrier_id=*/0, /*count=*/NUM_WARPS);
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rd_cycles_force(marker1);
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if (HW_TID() == 0) {
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#ifdef POWER
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PRINTF("\nstart %d end %d\n", marker0, marker1);
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#else
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PRINTF("\ncomplete\n");
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PRINTF("total cycles: %d\n", marker1 - marker0);
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for (int i = 0; i < dim_m; i += 8) {
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for (int j = 0; j < dim_n; j += 8) {
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PRINTF("%d %d ", (int) (C[i * dim_n + j]), (int) (C[i * dim_n + j + 4]));
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}
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PRINTF("\n");
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}
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#endif
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}
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}
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threadblock_barrier(/*barrier_id=*/0, /*count=*/NUM_WARPS);
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vx_tmc(0);
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}
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void kernel_body(int task_id, kernel_arg_t *__UNIFORM__ arg) {
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const int threadblock_id = task_id / NUM_THREADS_IN_CLUSTER;
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const int tid_in_threadblock = task_id % NUM_THREADS_IN_CLUSTER;
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thread_block_matmul_gemmini(arg, threadblock_id, tid_in_threadblock);
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}
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int main() {
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kernel_arg_t *arg = (kernel_arg_t *)KERNEL_ARG_DEV_MEM_ADDR;
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const uint32_t num_threads_in_cluster = NUM_THREADS_IN_CLUSTER;
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const uint32_t grid_size = num_threads_in_cluster * NUM_CLUSTERS;
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#ifdef RADIANCE
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vx_spawn_tasks_cluster(grid_size, (vx_spawn_tasks_cb)kernel_body, arg);
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#else
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// NOTE: This kernel assumes contiguous thread scheduling for efficient shared
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// memory allocation, and therefore does not work with original vx_spawn_tasks
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vx_spawn_tasks_contiguous(grid_size, (vx_spawn_tasks_cb)kernel_body, arg);
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#endif
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return 0;
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}
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