texunit tex_wrap

hw/rtl/cache/VX_bank.v

@@ -1,4 +1,4 @@
-`include "VX_cache_config.vh"
+`include "VX_cache_define.vh"
 
 module VX_bank #(
     parameter CACHE_ID                      = 0,

hw/rtl/cache/VX_cache.v

@@ -1,4 +1,4 @@
-`include "VX_cache_config.vh"
+`include "VX_cache_define.vh"
 
 module VX_cache #(
     parameter CACHE_ID                      = 0,

hw/rtl/cache/VX_cache_core_req_bank_sel.v

@@ -1,4 +1,4 @@
-`include "VX_cache_config.vh"
+`include "VX_cache_define.vh"
 
 module VX_cache_core_req_bank_sel #(  
     // Size of line inside a bank in bytes

hw/rtl/cache/VX_cache_core_rsp_merge.v

@@ -1,4 +1,4 @@
-`include "VX_cache_config.vh"
+`include "VX_cache_define.vh"
 
 module VX_cache_core_rsp_merge #(
     // Number of Word requests per cycle

hw/rtl/cache/VX_cache_define.vh

@@ -1,5 +1,5 @@
-`ifndef VX_CACHE_CONFIG
-`define VX_CACHE_CONFIG
+`ifndef VX_CACHE_DEFINE
+`define VX_CACHE_DEFINE
 
 `include "VX_platform.vh"
 

hw/rtl/cache/VX_data_access.v

@@ -1,4 +1,4 @@
-`include "VX_cache_config.vh"
+`include "VX_cache_define.vh"
 
 module VX_data_access #(
     parameter CACHE_ID          = 0,

hw/rtl/cache/VX_flush_ctrl.v

@@ -1,4 +1,4 @@
-`include "VX_cache_config.vh"
+`include "VX_cache_define.vh"
 
 module VX_flush_ctrl #(
     // Size of cache in bytes

hw/rtl/cache/VX_miss_resrv.v

@@ -1,4 +1,4 @@
-`include "VX_cache_config.vh"
+`include "VX_cache_define.vh"
 
 module VX_miss_resrv #(
     parameter CACHE_ID          = 0,

hw/rtl/cache/VX_shared_mem.v

@@ -1,4 +1,4 @@
-`include "VX_cache_config.vh"
+`include "VX_cache_define.vh"
 
 module VX_shared_mem #(
     parameter CACHE_ID                      = 0,

hw/rtl/cache/VX_tag_access.v

@@ -1,4 +1,4 @@
-`include "VX_cache_config.vh"
+`include "VX_cache_define.vh"
 
 module VX_tag_access #(
     parameter CACHE_ID          = 0,