From 1431ef9bc05eb0b1c0cdd9afc608427ccaabc8c9 Mon Sep 17 00:00:00 2001 From: Blaise Tine Date: Sat, 20 Mar 2021 13:40:42 -0400 Subject: [PATCH] texunit tex_wrap --- hw/rtl/VX_define.vh | 16 +---- hw/rtl/cache/VX_bank.v | 2 +- hw/rtl/cache/VX_cache.v | 2 +- hw/rtl/cache/VX_cache_core_req_bank_sel.v | 2 +- hw/rtl/cache/VX_cache_core_rsp_merge.v | 2 +- ...{VX_cache_config.vh => VX_cache_define.vh} | 4 +- hw/rtl/cache/VX_data_access.v | 2 +- hw/rtl/cache/VX_flush_ctrl.v | 2 +- hw/rtl/cache/VX_miss_resrv.v | 2 +- hw/rtl/cache/VX_shared_mem.v | 2 +- hw/rtl/cache/VX_tag_access.v | 2 +- hw/rtl/interfaces/VX_cache_dram_req_if.v | 2 +- hw/rtl/interfaces/VX_cache_dram_rsp_if.v | 2 +- hw/rtl/interfaces/VX_dcache_core_req_if.v | 2 +- hw/rtl/interfaces/VX_dcache_core_rsp_if.v | 2 +- hw/rtl/interfaces/VX_icache_core_req_if.v | 2 +- hw/rtl/interfaces/VX_icache_core_rsp_if.v | 2 +- hw/rtl/tex_unit/VX_tex_addr_gen.v | 71 ++++++++++++------- hw/rtl/tex_unit/VX_tex_define.vh | 25 +++++++ hw/rtl/tex_unit/VX_tex_format.v | 4 +- hw/rtl/tex_unit/VX_tex_memory.v | 2 +- hw/rtl/tex_unit/VX_tex_sampler.v | 2 +- hw/rtl/tex_unit/VX_tex_unit.v | 4 +- hw/rtl/tex_unit/VX_tex_wrap.v | 52 ++++++++++---- 24 files changed, 134 insertions(+), 76 deletions(-) rename hw/rtl/cache/{VX_cache_config.vh => VX_cache_define.vh} (98%) create mode 100644 hw/rtl/tex_unit/VX_tex_define.vh diff --git a/hw/rtl/VX_define.vh b/hw/rtl/VX_define.vh index 243a37b3..69763381 100644 --- a/hw/rtl/VX_define.vh +++ b/hw/rtl/VX_define.vh @@ -16,6 +16,8 @@ `define REQS_BITS `LOG2UP(NUM_REQS) +`define NTEX_BITS `LOG2UP(`NUM_TEX_UNITS) + `ifdef EXT_F_ENABLE `define NUM_REGS 64 `else @@ -387,19 +389,7 @@ `define XDRAM_TAG_WIDTH (`DDRAM_TAG_WIDTH+`CLOG2(2)) -////////////////////////// Texture Unit Configurable Knobs ////////////////////////////// - -`define NTEX_BITS `LOG2UP(`NUM_TEX_UNITS) - -`define TEX_ADDR_BITS 32 -`define TEX_FORMAT_BITS 3 -`define TEX_WRAP_BITS 2 -`define TEX_WIDTH_BITS 12 -`define TEX_HEIGHT_BITS 12 -`define TEX_STRIDE_BITS 2 -`define TEX_FILTER_BITS 1 - -//////////////////////////////////////////////////////////////////////////////////////// +/////////////////////////////////////////////////////////////////////////////// `include "VX_types.vh" diff --git a/hw/rtl/cache/VX_bank.v b/hw/rtl/cache/VX_bank.v index 7629b264..eda0bfb1 100644 --- a/hw/rtl/cache/VX_bank.v +++ b/hw/rtl/cache/VX_bank.v @@ -1,4 +1,4 @@ -`include "VX_cache_config.vh" +`include "VX_cache_define.vh" module VX_bank #( parameter CACHE_ID = 0, diff --git a/hw/rtl/cache/VX_cache.v b/hw/rtl/cache/VX_cache.v index 63133664..50d2ec7c 100644 --- a/hw/rtl/cache/VX_cache.v +++ b/hw/rtl/cache/VX_cache.v @@ -1,4 +1,4 @@ -`include "VX_cache_config.vh" +`include "VX_cache_define.vh" module VX_cache #( parameter CACHE_ID = 0, diff --git a/hw/rtl/cache/VX_cache_core_req_bank_sel.v b/hw/rtl/cache/VX_cache_core_req_bank_sel.v index 183ff6c2..dd75bfe7 100644 --- a/hw/rtl/cache/VX_cache_core_req_bank_sel.v +++ b/hw/rtl/cache/VX_cache_core_req_bank_sel.v @@ -1,4 +1,4 @@ -`include "VX_cache_config.vh" +`include "VX_cache_define.vh" module VX_cache_core_req_bank_sel #( // Size of line inside a bank in bytes diff --git a/hw/rtl/cache/VX_cache_core_rsp_merge.v b/hw/rtl/cache/VX_cache_core_rsp_merge.v index dad89c15..5c38f2e4 100644 --- a/hw/rtl/cache/VX_cache_core_rsp_merge.v +++ b/hw/rtl/cache/VX_cache_core_rsp_merge.v @@ -1,4 +1,4 @@ -`include "VX_cache_config.vh" +`include "VX_cache_define.vh" module VX_cache_core_rsp_merge #( // Number of Word requests per cycle diff --git a/hw/rtl/cache/VX_cache_config.vh b/hw/rtl/cache/VX_cache_define.vh similarity index 98% rename from hw/rtl/cache/VX_cache_config.vh rename to hw/rtl/cache/VX_cache_define.vh index bfe8b96c..e205d7ad 100644 --- a/hw/rtl/cache/VX_cache_config.vh +++ b/hw/rtl/cache/VX_cache_define.vh @@ -1,5 +1,5 @@ -`ifndef VX_CACHE_CONFIG -`define VX_CACHE_CONFIG +`ifndef VX_CACHE_DEFINE +`define VX_CACHE_DEFINE `include "VX_platform.vh" diff --git a/hw/rtl/cache/VX_data_access.v b/hw/rtl/cache/VX_data_access.v index fbec1107..265fa327 100644 --- a/hw/rtl/cache/VX_data_access.v +++ b/hw/rtl/cache/VX_data_access.v @@ -1,4 +1,4 @@ -`include "VX_cache_config.vh" +`include "VX_cache_define.vh" module VX_data_access #( parameter CACHE_ID = 0, diff --git a/hw/rtl/cache/VX_flush_ctrl.v b/hw/rtl/cache/VX_flush_ctrl.v index 261197b6..b204cc7b 100644 --- a/hw/rtl/cache/VX_flush_ctrl.v +++ b/hw/rtl/cache/VX_flush_ctrl.v @@ -1,4 +1,4 @@ -`include "VX_cache_config.vh" +`include "VX_cache_define.vh" module VX_flush_ctrl #( // Size of cache in bytes diff --git a/hw/rtl/cache/VX_miss_resrv.v b/hw/rtl/cache/VX_miss_resrv.v index 55755d61..6bf3aa8c 100644 --- a/hw/rtl/cache/VX_miss_resrv.v +++ b/hw/rtl/cache/VX_miss_resrv.v @@ -1,4 +1,4 @@ -`include "VX_cache_config.vh" +`include "VX_cache_define.vh" module VX_miss_resrv #( parameter CACHE_ID = 0, diff --git a/hw/rtl/cache/VX_shared_mem.v b/hw/rtl/cache/VX_shared_mem.v index 4d9eee57..7d500733 100644 --- a/hw/rtl/cache/VX_shared_mem.v +++ b/hw/rtl/cache/VX_shared_mem.v @@ -1,4 +1,4 @@ -`include "VX_cache_config.vh" +`include "VX_cache_define.vh" module VX_shared_mem #( parameter CACHE_ID = 0, diff --git a/hw/rtl/cache/VX_tag_access.v b/hw/rtl/cache/VX_tag_access.v index 829f4006..ef2c6347 100644 --- a/hw/rtl/cache/VX_tag_access.v +++ b/hw/rtl/cache/VX_tag_access.v @@ -1,4 +1,4 @@ -`include "VX_cache_config.vh" +`include "VX_cache_define.vh" module VX_tag_access #( parameter CACHE_ID = 0, diff --git a/hw/rtl/interfaces/VX_cache_dram_req_if.v b/hw/rtl/interfaces/VX_cache_dram_req_if.v index 5591bf9f..9bebf8ef 100644 --- a/hw/rtl/interfaces/VX_cache_dram_req_if.v +++ b/hw/rtl/interfaces/VX_cache_dram_req_if.v @@ -1,7 +1,7 @@ `ifndef VX_CACHE_DRAM_REQ_IF `define VX_CACHE_DRAM_REQ_IF -`include "../cache/VX_cache_config.vh" +`include "../cache/VX_cache_define.vh" interface VX_cache_dram_req_if #( parameter DRAM_LINE_WIDTH = 1, diff --git a/hw/rtl/interfaces/VX_cache_dram_rsp_if.v b/hw/rtl/interfaces/VX_cache_dram_rsp_if.v index 2a3d15e0..bae0d29d 100644 --- a/hw/rtl/interfaces/VX_cache_dram_rsp_if.v +++ b/hw/rtl/interfaces/VX_cache_dram_rsp_if.v @@ -1,7 +1,7 @@ `ifndef VX_CACHE_DRAM_RSP_IF `define VX_CACHE_DRAM_RSP_IF -`include "../cache/VX_cache_config.vh" +`include "../cache/VX_cache_define.vh" interface VX_cache_dram_rsp_if #( parameter DRAM_LINE_WIDTH = 1, diff --git a/hw/rtl/interfaces/VX_dcache_core_req_if.v b/hw/rtl/interfaces/VX_dcache_core_req_if.v index bfc640f2..f1774fdb 100644 --- a/hw/rtl/interfaces/VX_dcache_core_req_if.v +++ b/hw/rtl/interfaces/VX_dcache_core_req_if.v @@ -1,7 +1,7 @@ `ifndef VX_DCACHE_CORE_REQ_IF `define VX_DCACHE_CORE_REQ_IF -`include "../cache/VX_cache_config.vh" +`include "../cache/VX_cache_define.vh" interface VX_dcache_core_req_if #( parameter LANES = 1, diff --git a/hw/rtl/interfaces/VX_dcache_core_rsp_if.v b/hw/rtl/interfaces/VX_dcache_core_rsp_if.v index bf6b3fc1..4d17d24a 100644 --- a/hw/rtl/interfaces/VX_dcache_core_rsp_if.v +++ b/hw/rtl/interfaces/VX_dcache_core_rsp_if.v @@ -1,7 +1,7 @@ `ifndef VX_DCACHE_CORE_RSP_IF `define VX_DCACHE_CORE_RSP_IF -`include "../cache/VX_cache_config.vh" +`include "../cache/VX_cache_define.vh" interface VX_dcache_core_rsp_if #( parameter LANES = 1, diff --git a/hw/rtl/interfaces/VX_icache_core_req_if.v b/hw/rtl/interfaces/VX_icache_core_req_if.v index 2edb05d9..550e597c 100644 --- a/hw/rtl/interfaces/VX_icache_core_req_if.v +++ b/hw/rtl/interfaces/VX_icache_core_req_if.v @@ -1,7 +1,7 @@ `ifndef VX_ICACHE_CORE_REQ_IF `define VX_ICACHE_CORE_REQ_IF -`include "../cache/VX_cache_config.vh" +`include "../cache/VX_cache_define.vh" interface VX_icache_core_req_if #( parameter WORD_SIZE = 1, diff --git a/hw/rtl/interfaces/VX_icache_core_rsp_if.v b/hw/rtl/interfaces/VX_icache_core_rsp_if.v index 54ffa56d..75ebcc1e 100644 --- a/hw/rtl/interfaces/VX_icache_core_rsp_if.v +++ b/hw/rtl/interfaces/VX_icache_core_rsp_if.v @@ -1,7 +1,7 @@ `ifndef VX_ICACHE_CORE_RSP_IF `define VX_ICACHE_CORE_RSP_IF -`include "../cache/VX_cache_config.vh" +`include "../cache/VX_cache_define.vh" interface VX_icache_core_rsp_if #( parameter WORD_SIZE = 1, diff --git a/hw/rtl/tex_unit/VX_tex_addr_gen.v b/hw/rtl/tex_unit/VX_tex_addr_gen.v index 8b0cbe17..f29a21ef 100644 --- a/hw/rtl/tex_unit/VX_tex_addr_gen.v +++ b/hw/rtl/tex_unit/VX_tex_addr_gen.v @@ -1,10 +1,8 @@ -`include "VX_define.vh" +`include "VX_tex_define.vh" module VX_tex_addr_gen #( - parameter CORE_ID = 0, - parameter REQ_TAG_WIDTH = 1, - parameter FRAC_BITS = 20, - parameter INT_BITS = 32 - FRAC_BITS + parameter CORE_ID = 0, + parameter REQ_TAG_WIDTH = 1 ) ( input wire clk, input wire reset, @@ -16,17 +14,17 @@ module VX_tex_addr_gen #( // inputs - input wire [`NUM_THREADS-1:0] req_tmask, - input wire [REQ_TAG_WIDTH-1:0] req_tag, + input wire [`NUM_THREADS-1:0] req_tmask, + input wire [REQ_TAG_WIDTH-1:0] req_tag, - input wire [`TEX_FILTER_BITS-1:0] filter, - input wire [`TEX_WRAP_BITS-1:0] wrap_u, - input wire [`TEX_WRAP_BITS-1:0] wrap_v, + input wire [`TEX_FILTER_BITS-1:0] filter, + input wire [`TEX_WRAP_BITS-1:0] wrap_u, + input wire [`TEX_WRAP_BITS-1:0] wrap_v, - input wire [`TEX_ADDR_BITS-1:0] base_addr, - input wire [`TEX_STRIDE_BITS-1:0] log2_stride, - input wire [`TEX_WIDTH_BITS-1:0] log2_width, - input wire [`TEX_HEIGHT_BITS-1:0] log2_height, + input wire [`TEX_ADDR_BITS-1:0] base_addr, + input wire [`TEX_STRIDE_BITS-1:0] log2_stride, + input wire [`TEX_WIDTH_BITS-1:0] log2_width, + input wire [`TEX_HEIGHT_BITS-1:0] log2_height, input wire [`NUM_THREADS-1:0][31:0] coord_u, input wire [`NUM_THREADS-1:0][31:0] coord_v, @@ -43,23 +41,44 @@ module VX_tex_addr_gen #( ); `UNUSED_PARAM (CORE_ID) - - /*`UNUSED_VAR (filter) `UNUSED_VAR (lod) - wire [31:0] u, y; - wire [31:0] x_offset, y_offset; - wire [31:0] addr0; + for (genvar i = 0; i < `NUM_THREADS; ++i) begin - // addressing mode + // addressing mode + + wire [31:0] u, v; + VX_tex_wrap #( + .CORE_ID (CORE_ID) + ) tex_wrap_u ( + .wrap_i (wrap_u), + .coord_i (coord_u[i]), + .coord_o (u) + ); - assign x_offset = u >> (5'(FRAC_BITS) - log2_width); - assign y_offset = v >> (5'(FRAC_BITS) - log2_height); - assign addr0 = base_addr + (x_offset + (y_offset << log2_width)) << log2_stride; + VX_tex_wrap #( + .CORE_ID (CORE_ID) + ) tex_wrap_v ( + .wrap_i (wrap_v), + .coord_i (coord_v[i]), + .coord_o (v) + ); - wire [3:0] req_valids = 4'(valid_in); - wire [3:0][31:0] req_address = {4{addr0}}; + // texel addresses generation + + wire [31:0] x_offset, y_offset; + wire [31:0] addr0; + + assign x_offset = u >> (5'(`FIXED_FRAC) - log2_width); + assign y_offset = v >> (5'(`FIXED_FRAC) - log2_height); + assign addr0 = base_addr + (x_offset + (y_offset << log2_width)) << log2_stride; + + wire [3:0] req_valids = 4'(valid_in); + wire [3:0][31:0] req_address = {4{addr0}}; + end + + wire stall_out = mem_req_valid && ~mem_req_ready; VX_pipe_register #( .DATAW (1 + 4 + 4 * 32 + REQ_TAG_WIDTH), @@ -72,6 +91,6 @@ module VX_tex_addr_gen #( .data_out ({mem_req_valid, mem_req_addr, mem_req_tag}) ); - assign ready_in = ~stall_out;*/ + assign ready_in = ~stall_out; endmodule \ No newline at end of file diff --git a/hw/rtl/tex_unit/VX_tex_define.vh b/hw/rtl/tex_unit/VX_tex_define.vh new file mode 100644 index 00000000..81872eba --- /dev/null +++ b/hw/rtl/tex_unit/VX_tex_define.vh @@ -0,0 +1,25 @@ +`ifndef VX_TEX_DEFINE +`define VX_TEX_DEFINE + +`include "VX_define.vh" + +`define FIXED_FRAC 20 +`define FIXED_INT (32 - `FIXED_FRAC) +`define FIXED_ONE (1 << `FIXED_FRAC) +`define FIXED_MASK (`FIXED_ONE - 1) + +`define CLAMP(x,lo,hi) ((x < lo) ? lo : ((x > hi) ? hi : x)) + +`define TEX_ADDR_BITS 32 +`define TEX_FORMAT_BITS 3 +`define TEX_WRAP_BITS 2 +`define TEX_WIDTH_BITS 12 +`define TEX_HEIGHT_BITS 12 +`define TEX_STRIDE_BITS 2 +`define TEX_FILTER_BITS 1 + +`define TEX_WRAP_REPEAT 0 +`define TEX_WRAP_CLAMP 1 +`define TEX_WRAP_MIRROR 2 + +`endif \ No newline at end of file diff --git a/hw/rtl/tex_unit/VX_tex_format.v b/hw/rtl/tex_unit/VX_tex_format.v index 8e713110..724664ec 100644 --- a/hw/rtl/tex_unit/VX_tex_format.v +++ b/hw/rtl/tex_unit/VX_tex_format.v @@ -1,8 +1,10 @@ +`include "VX_tex_define.vh" + module VX_tex_format #( parameter CORE_ID = 0 ) ( // TODO -) +); `UNUSED_PARAM (CORE_ID) // TODO diff --git a/hw/rtl/tex_unit/VX_tex_memory.v b/hw/rtl/tex_unit/VX_tex_memory.v index 26abf69e..77e5d018 100644 --- a/hw/rtl/tex_unit/VX_tex_memory.v +++ b/hw/rtl/tex_unit/VX_tex_memory.v @@ -1,4 +1,4 @@ -`include "VX_define.vh" +`include "VX_tex_define.vh" module VX_tex_memory #( parameter CORE_ID = 0, diff --git a/hw/rtl/tex_unit/VX_tex_sampler.v b/hw/rtl/tex_unit/VX_tex_sampler.v index 60a1ba4c..1271c063 100644 --- a/hw/rtl/tex_unit/VX_tex_sampler.v +++ b/hw/rtl/tex_unit/VX_tex_sampler.v @@ -1,4 +1,4 @@ -`include "VX_define.vh" +`include "VX_tex_define.vh" module VX_tex_sampler #( parameter CORE_ID = 0 diff --git a/hw/rtl/tex_unit/VX_tex_unit.v b/hw/rtl/tex_unit/VX_tex_unit.v index 292fabe0..3bcd0410 100644 --- a/hw/rtl/tex_unit/VX_tex_unit.v +++ b/hw/rtl/tex_unit/VX_tex_unit.v @@ -1,5 +1,4 @@ -`include "VX_platform.vh" -`include "VX_define.vh" +`include "VX_tex_define.vh" module VX_tex_unit #( parameter CORE_ID = 0 @@ -83,7 +82,6 @@ module VX_tex_unit #( wire mem_rsp_ready; VX_tex_addr_gen #( - .FRAC_BITS (20), .REQ_TAG_WIDTH (REQ_TAG_WIDTH) ) tex_addr_gen ( .clk (clk), diff --git a/hw/rtl/tex_unit/VX_tex_wrap.v b/hw/rtl/tex_unit/VX_tex_wrap.v index 3fce0543..5c536a68 100644 --- a/hw/rtl/tex_unit/VX_tex_wrap.v +++ b/hw/rtl/tex_unit/VX_tex_wrap.v @@ -1,25 +1,49 @@ -`include "VX_define.vh" +`include "VX_tex_define.vh" + +/* +switch(addressing_mode) { +case undefined: return is_undefined; +case clamp_to_edge: return intdowni(max(0, min(coord, coorddim - 1))); +case clamp_to_border: return is_border; +case repeat: + tile = intdowni(coord / coorddim); + return intdowni(coord - (tile * coorddim)); +case mirrored_repeat: + mirrored_coord = (coord < 0) ? (-coord - 1) : coord; + tile = intdowni(mirrored_coord / coorddim); + mirrored_coord = intdowni(mirrored_coord - (tile * coorddim)); + if (tile & 1) { + mirrored_coord = (coorddim - 1) - mirrored_coord; + } + return mirrored_coord; +} +*/ module VX_tex_wrap #( - parameter CORE_ID = 0, - parameter FRAC_BITS = 20, - parameter INT_BITS = 32 - FRAC_BITS + parameter CORE_ID = 0 ) ( - input wire [`TEX_WRAP_BITS-1:0] wrap_i; + input wire [`TEX_WRAP_BITS-1:0] wrap_i, input wire [31:0] coord_i, - input wire [31:0] coord_o -) + input wire [`FIXED_FRAC-1:0] coord_o +); `UNUSED_PARAM (CORE_ID) - /*always @(*) begin + reg [31:0] coord_r; + + wire [31:0] clamp = `CLAMP(coord_i, 0, `FIXED_MASK); + + always @(*) begin case (wrap_i) - `ALU_AND: msc_result[i] = alu_in1[i] & alu_in2_imm[i]; - `ALU_OR: msc_result[i] = alu_in1[i] | alu_in2_imm[i]; - `ALU_XOR: msc_result[i] = alu_in1[i] ^ alu_in2_imm[i]; - //`ALU_SLL, - default: msc_result[i] = alu_in1[i] << alu_in2_imm[i][4:0]; + `TEX_WRAP_CLAMP: + coord_r = clamp[`FIXED_FRAC-1:0]; + `TEX_WRAP_MIRROR: + coord_r = coord_i[`FIXED_FRAC-1:0] ^ {`FIXED_FRAC{coord_i[`FIXED_FRAC]}}; + default: //`TEX_WRAP_REPEAT + coord_r = coord_i[`FIXED_FRAC-1:0]; endcase - end*/ + end + + assign coord_o = coord_r; endmodule \ No newline at end of file