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RTL code refactoring

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This commit is contained in:
Blaise Tine
2020-04-20 08:01:46 -04:00
parent 62c1c3fdbb
commit 0c81a3ae19
10 changed files with 94 additions and 94 deletions
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6
hw/rtl/interfaces/VX_gpu_dcache_req_if.v
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@@ -9,10 +9,10 @@ interface VX_gpu_dcache_req_if #(
// Core request
wire [NUM_REQUESTS-1:0] core_req_valid;
wire [NUM_REQUESTS-1:0][2:0] core_req_mem_read;
wire [NUM_REQUESTS-1:0][2:0] core_req_mem_write;
wire [NUM_REQUESTS-1:0][2:0] core_req_read;
wire [NUM_REQUESTS-1:0][2:0] core_req_write;
wire [NUM_REQUESTS-1:0][31:0] core_req_addr;
wire [NUM_REQUESTS-1:0][31:0] core_req_writedata;
wire [NUM_REQUESTS-1:0][31:0] core_req_data;
wire core_req_ready;
// Core request Meta data

8
hw/rtl/interfaces/VX_gpu_dcache_rsp_if.v
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@@ -10,11 +10,11 @@ interface VX_gpu_dcache_rsp_if #(
// Core response
wire [NUM_REQUESTS-1:0] core_rsp_valid;
`IGNORE_WARNINGS_BEGIN
wire [4:0] core_rsp_req_rd;
wire [1:0] core_rsp_req_wb;
wire [4:0] core_rsp_read;
wire [1:0] core_rsp_write;
`IGNORE_WARNINGS_END
wire [NUM_REQUESTS-1:0][31:0] core_rsp_pc;
wire [NUM_REQUESTS-1:0][31:0] core_rsp_readdata;
//wire [NUM_REQUESTS-1:0][31:0] core_rsp_pc;
wire [NUM_REQUESTS-1:0][31:0] core_rsp_data;
wire core_rsp_ready;
// Core response meta data