From 0c81a3ae194c7523108eb70436fb15994133eba3 Mon Sep 17 00:00:00 2001 From: Blaise Tine Date: Mon, 20 Apr 2020 08:01:46 -0400 Subject: [PATCH] RTL code refactoring --- hw/rtl/VX_dmem_controller.v | 64 ++++++++++---------- hw/rtl/VX_icache_stage.v | 8 +-- hw/rtl/VX_lsu.v | 12 ++-- hw/rtl/Vortex.v | 10 +-- hw/rtl/Vortex_Cluster.v | 14 ++--- hw/rtl/Vortex_Socket.v | 14 ++--- hw/rtl/generic_cache/VX_cache.v | 28 ++++----- hw/rtl/generic_cache/VX_cache_wb_sel_merge.v | 24 ++++---- hw/rtl/interfaces/VX_gpu_dcache_req_if.v | 6 +- hw/rtl/interfaces/VX_gpu_dcache_rsp_if.v | 8 +-- 10 files changed, 94 insertions(+), 94 deletions(-) diff --git a/hw/rtl/VX_dmem_controller.v b/hw/rtl/VX_dmem_controller.v index 9a8fddbe..55c049de 100644 --- a/hw/rtl/VX_dmem_controller.v +++ b/hw/rtl/VX_dmem_controller.v @@ -34,10 +34,10 @@ module VX_dmem_controller ( // Dcache Request assign dcache_req_dcache_if.core_req_valid = dcache_req_if.core_req_valid & {`NUM_THREADS{~to_shm}}; - assign dcache_req_dcache_if.core_req_mem_read = dcache_req_if.core_req_mem_read; - assign dcache_req_dcache_if.core_req_mem_write = dcache_req_if.core_req_mem_write; + assign dcache_req_dcache_if.core_req_read = dcache_req_if.core_req_read; + assign dcache_req_dcache_if.core_req_write = dcache_req_if.core_req_write; assign dcache_req_dcache_if.core_req_addr = dcache_req_if.core_req_addr; - assign dcache_req_dcache_if.core_req_writedata = dcache_req_if.core_req_writedata; + assign dcache_req_dcache_if.core_req_data = dcache_req_if.core_req_data; assign dcache_req_dcache_if.core_req_rd = dcache_req_if.core_req_rd; assign dcache_req_dcache_if.core_req_wb = dcache_req_if.core_req_wb; assign dcache_req_dcache_if.core_req_warp_num = dcache_req_if.core_req_warp_num; @@ -48,9 +48,9 @@ module VX_dmem_controller ( // Shared Memory Request assign dcache_req_smem_if.core_req_valid = dcache_req_if.core_req_valid & {`NUM_THREADS{to_shm}}; assign dcache_req_smem_if.core_req_addr = dcache_req_if.core_req_addr; - assign dcache_req_smem_if.core_req_writedata = dcache_req_if.core_req_writedata; - assign dcache_req_smem_if.core_req_mem_read = dcache_req_if.core_req_mem_read; - assign dcache_req_smem_if.core_req_mem_write = dcache_req_if.core_req_mem_write; + assign dcache_req_smem_if.core_req_data = dcache_req_if.core_req_data; + assign dcache_req_smem_if.core_req_read = dcache_req_if.core_req_read; + assign dcache_req_smem_if.core_req_write = dcache_req_if.core_req_write; assign dcache_req_smem_if.core_req_rd = dcache_req_if.core_req_rd; assign dcache_req_smem_if.core_req_wb = dcache_req_if.core_req_wb; assign dcache_req_smem_if.core_req_warp_num = dcache_req_if.core_req_warp_num; @@ -60,13 +60,13 @@ module VX_dmem_controller ( // Dcache Response assign dcache_rsp_if.core_rsp_valid = dcache_wants_wb ? dcache_rsp_dcache_if.core_rsp_valid : dcache_rsp_smem_if.core_rsp_valid; - assign dcache_rsp_if.core_rsp_req_rd = dcache_wants_wb ? dcache_rsp_dcache_if.core_rsp_req_rd : dcache_rsp_smem_if.core_rsp_req_rd; - assign dcache_rsp_if.core_rsp_req_wb = dcache_wants_wb ? dcache_rsp_dcache_if.core_rsp_req_wb : dcache_rsp_smem_if.core_rsp_req_wb; + assign dcache_rsp_if.core_rsp_read = dcache_wants_wb ? dcache_rsp_dcache_if.core_rsp_read : dcache_rsp_smem_if.core_rsp_read; + assign dcache_rsp_if.core_rsp_write = dcache_wants_wb ? dcache_rsp_dcache_if.core_rsp_write : dcache_rsp_smem_if.core_rsp_write; assign dcache_rsp_if.core_rsp_pc = dcache_wants_wb ? dcache_rsp_dcache_if.core_rsp_pc : dcache_rsp_smem_if.core_rsp_pc; - assign dcache_rsp_if.core_rsp_readdata = dcache_wants_wb ? dcache_rsp_dcache_if.core_rsp_readdata : dcache_rsp_smem_if.core_rsp_readdata; + assign dcache_rsp_if.core_rsp_data = dcache_wants_wb ? dcache_rsp_dcache_if.core_rsp_data : dcache_rsp_smem_if.core_rsp_data; assign dcache_rsp_if.core_rsp_warp_num = dcache_wants_wb ? dcache_rsp_dcache_if.core_rsp_warp_num : dcache_rsp_smem_if.core_rsp_warp_num; - assign dcache_req_if.core_req_ready = to_shm ? dcache_req_smem_if.core_req_ready : dcache_req_dcache_if.core_req_ready; + assign dcache_req_if.core_req_ready = to_shm ? dcache_req_smem_if.core_req_ready : dcache_req_dcache_if.core_req_ready; VX_gpu_dcache_dram_req_if #(.BANK_LINE_WORDS(`DBANK_LINE_WORDS)) gpu_smem_dram_req_if(); VX_gpu_dcache_dram_rsp_if #(.BANK_LINE_WORDS(`DBANK_LINE_WORDS)) gpu_smem_dram_res_if(); @@ -98,10 +98,10 @@ module VX_dmem_controller ( // Core req .core_req_valid (dcache_req_smem_if.core_req_valid), - .core_req_mem_read (dcache_req_smem_if.core_req_mem_read), - .core_req_mem_write (dcache_req_smem_if.core_req_mem_write), + .core_req_read (dcache_req_smem_if.core_req_read), + .core_req_write (dcache_req_smem_if.core_req_write), .core_req_addr (dcache_req_smem_if.core_req_addr), - .core_req_writedata (dcache_req_smem_if.core_req_writedata), + .core_req_data (dcache_req_smem_if.core_req_data), .core_req_rd (dcache_req_smem_if.core_req_rd), .core_req_wb (dcache_req_smem_if.core_req_wb), .core_req_warp_num (dcache_req_smem_if.core_req_warp_num), @@ -115,13 +115,13 @@ module VX_dmem_controller ( // Cache CWB .core_rsp_valid (dcache_rsp_smem_if.core_rsp_valid), - .core_rsp_req_rd (dcache_rsp_smem_if.core_rsp_req_rd), - .core_rsp_req_wb (dcache_rsp_smem_if.core_rsp_req_wb), + .core_rsp_read (dcache_rsp_smem_if.core_rsp_read), + .core_rsp_write (dcache_rsp_smem_if.core_rsp_write), .core_rsp_warp_num (dcache_rsp_smem_if.core_rsp_warp_num), - .core_rsp_readdata (dcache_rsp_smem_if.core_rsp_readdata), + .core_rsp_data (dcache_rsp_smem_if.core_rsp_data), .core_rsp_pc (dcache_rsp_smem_if.core_rsp_pc), `IGNORE_WARNINGS_BEGIN - .core_rsp_address (), + .core_rsp_addr (), `IGNORE_WARNINGS_END // DRAM response @@ -181,10 +181,10 @@ module VX_dmem_controller ( // Core req .core_req_valid (dcache_req_dcache_if.core_req_valid), - .core_req_mem_read (dcache_req_dcache_if.core_req_mem_read), - .core_req_mem_write (dcache_req_dcache_if.core_req_mem_write), + .core_req_read (dcache_req_dcache_if.core_req_read), + .core_req_write (dcache_req_dcache_if.core_req_write), .core_req_addr (dcache_req_dcache_if.core_req_addr), - .core_req_writedata (dcache_req_dcache_if.core_req_writedata), + .core_req_data (dcache_req_dcache_if.core_req_data), .core_req_rd (dcache_req_dcache_if.core_req_rd), .core_req_wb (dcache_req_dcache_if.core_req_wb), .core_req_warp_num (dcache_req_dcache_if.core_req_warp_num), @@ -198,13 +198,13 @@ module VX_dmem_controller ( // Cache CWB .core_rsp_valid (dcache_rsp_dcache_if.core_rsp_valid), - .core_rsp_req_rd (dcache_rsp_dcache_if.core_rsp_req_rd), - .core_rsp_req_wb (dcache_rsp_dcache_if.core_rsp_req_wb), + .core_rsp_read (dcache_rsp_dcache_if.core_rsp_read), + .core_rsp_write (dcache_rsp_dcache_if.core_rsp_write), .core_rsp_warp_num (dcache_rsp_dcache_if.core_rsp_warp_num), - .core_rsp_readdata (dcache_rsp_dcache_if.core_rsp_readdata), + .core_rsp_data (dcache_rsp_dcache_if.core_rsp_data), .core_rsp_pc (dcache_rsp_dcache_if.core_rsp_pc), `IGNORE_WARNINGS_BEGIN - .core_rsp_address (), + .core_rsp_addr (), `IGNORE_WARNINGS_END // DRAM response @@ -220,7 +220,7 @@ module VX_dmem_controller ( .dram_req_write (gpu_dcache_dram_req_if.dram_req_write), .dram_req_addr (gpu_dcache_dram_req_if.dram_req_addr), .dram_req_data (gpu_dcache_dram_req_if.dram_req_data), - .dram_req_ready (gpu_dcache_dram_req_if.dram_req_ready), + .dram_req_ready (gpu_dcache_dram_req_if.dram_req_ready), // Snoop Request .snp_req_valid (gpu_dcache_snp_req_if.snp_req_valid), @@ -262,10 +262,10 @@ module VX_dmem_controller ( // Core req .core_req_valid (icache_req_if.core_req_valid), - .core_req_mem_read (icache_req_if.core_req_mem_read), - .core_req_mem_write (icache_req_if.core_req_mem_write), + .core_req_read (icache_req_if.core_req_read), + .core_req_write (icache_req_if.core_req_write), .core_req_addr (icache_req_if.core_req_addr), - .core_req_writedata (icache_req_if.core_req_writedata), + .core_req_data (icache_req_if.core_req_data), .core_req_rd (icache_req_if.core_req_rd), .core_req_wb (icache_req_if.core_req_wb), .core_req_warp_num (icache_req_if.core_req_warp_num), @@ -279,13 +279,13 @@ module VX_dmem_controller ( // Cache CWB .core_rsp_valid (icache_rsp_if.core_rsp_valid), - .core_rsp_req_rd (icache_rsp_if.core_rsp_req_rd), - .core_rsp_req_wb (icache_rsp_if.core_rsp_req_wb), + .core_rsp_read (icache_rsp_if.core_rsp_read), + .core_rsp_write (icache_rsp_if.core_rsp_write), .core_rsp_warp_num (icache_rsp_if.core_rsp_warp_num), - .core_rsp_readdata (icache_rsp_if.core_rsp_readdata), + .core_rsp_data (icache_rsp_if.core_rsp_data), .core_rsp_pc (icache_rsp_if.core_rsp_pc), `IGNORE_WARNINGS_BEGIN - .core_rsp_address (), + .core_rsp_addr (), `IGNORE_WARNINGS_END // DRAM response diff --git a/hw/rtl/VX_icache_stage.v b/hw/rtl/VX_icache_stage.v index 3fb9d10e..0e06907b 100644 --- a/hw/rtl/VX_icache_stage.v +++ b/hw/rtl/VX_icache_stage.v @@ -21,15 +21,15 @@ module VX_icache_stage ( // Icache Request assign icache_req_if.core_req_valid = valid_inst && !total_freeze; assign icache_req_if.core_req_addr = fe_inst_meta_fi.inst_pc; - assign icache_req_if.core_req_writedata = 32'b0; - assign icache_req_if.core_req_mem_read = `LW_MEM_READ; - assign icache_req_if.core_req_mem_write = `NO_MEM_WRITE; + assign icache_req_if.core_req_data = 32'b0; + assign icache_req_if.core_req_read = `LW_MEM_READ; + assign icache_req_if.core_req_write = `NO_MEM_WRITE; assign icache_req_if.core_req_rd = 5'b0; assign icache_req_if.core_req_wb = {1{2'b1}}; assign icache_req_if.core_req_warp_num = fe_inst_meta_fi.warp_num; assign icache_req_if.core_req_pc = fe_inst_meta_fi.inst_pc; - assign fe_inst_meta_id.instruction = icache_rsp_if.core_rsp_readdata[0][31:0]; + assign fe_inst_meta_id.instruction = icache_rsp_if.core_rsp_data[0][31:0]; assign fe_inst_meta_id.inst_pc = icache_rsp_if.core_rsp_pc[0]; assign fe_inst_meta_id.warp_num = icache_rsp_if.core_rsp_warp_num; diff --git a/hw/rtl/VX_lsu.v b/hw/rtl/VX_lsu.v index bc8706ff..560a7225 100644 --- a/hw/rtl/VX_lsu.v +++ b/hw/rtl/VX_lsu.v @@ -47,9 +47,9 @@ module VX_lsu ( // Core Request assign dcache_req_if.core_req_valid = use_valid; assign dcache_req_if.core_req_addr = use_address; - assign dcache_req_if.core_req_writedata = use_store_data; - assign dcache_req_if.core_req_mem_read = {`NUM_THREADS{use_mem_read}}; - assign dcache_req_if.core_req_mem_write = {`NUM_THREADS{use_mem_write}}; + assign dcache_req_if.core_req_data = use_store_data; + assign dcache_req_if.core_req_read = {`NUM_THREADS{use_mem_read}}; + assign dcache_req_if.core_req_write = {`NUM_THREADS{use_mem_write}}; assign dcache_req_if.core_req_rd = use_rd; assign dcache_req_if.core_req_wb = {`NUM_THREADS{use_wb}}; assign dcache_req_if.core_req_warp_num = use_warp_num; @@ -62,11 +62,11 @@ module VX_lsu ( assign out_delay = ~dcache_req_if.core_req_ready; // Core Response - assign mem_wb_if.rd = dcache_rsp_if.core_rsp_req_rd; - assign mem_wb_if.wb = dcache_rsp_if.core_rsp_req_wb; + assign mem_wb_if.rd = dcache_rsp_if.core_rsp_read; + assign mem_wb_if.wb = dcache_rsp_if.core_rsp_write; assign mem_wb_if.wb_valid = dcache_rsp_if.core_rsp_valid; assign mem_wb_if.wb_warp_num = dcache_rsp_if.core_rsp_warp_num; - assign mem_wb_if.loaded_data = dcache_rsp_if.core_rsp_readdata; + assign mem_wb_if.loaded_data = dcache_rsp_if.core_rsp_data; wire[(`LOG2UP(`NUM_THREADS))-1:0] use_pc_index; diff --git a/hw/rtl/Vortex.v b/hw/rtl/Vortex.v index c2200671..cbbec006 100644 --- a/hw/rtl/Vortex.v +++ b/hw/rtl/Vortex.v @@ -82,18 +82,18 @@ module Vortex #( wire temp_io_valid = (!memory_delay) && (|dcache_req_if.core_req_valid) - && (dcache_req_if.core_req_mem_write[0] != `NO_MEM_WRITE) + && (dcache_req_if.core_req_write[0] != `NO_MEM_WRITE) && (dcache_req_if.core_req_addr[0] == `IO_BUS_ADDR); - wire [31:0] temp_io_data = dcache_req_if.core_req_writedata[0]; + wire [31:0] temp_io_data = dcache_req_if.core_req_data[0]; assign io_valid = temp_io_valid; assign io_data = temp_io_data; assign dcache_req_qual_if.core_req_valid = dcache_req_if.core_req_valid & {`NUM_THREADS{~io_valid}}; - assign dcache_req_qual_if.core_req_mem_read = dcache_req_if.core_req_mem_read; - assign dcache_req_qual_if.core_req_mem_write = dcache_req_if.core_req_mem_write; + assign dcache_req_qual_if.core_req_read = dcache_req_if.core_req_read; + assign dcache_req_qual_if.core_req_write = dcache_req_if.core_req_write; assign dcache_req_qual_if.core_req_addr = dcache_req_if.core_req_addr; - assign dcache_req_qual_if.core_req_writedata = dcache_req_if.core_req_writedata; + assign dcache_req_qual_if.core_req_data = dcache_req_if.core_req_data; assign dcache_req_if.core_req_ready = dcache_req_qual_if.core_req_ready; diff --git a/hw/rtl/Vortex_Cluster.v b/hw/rtl/Vortex_Cluster.v index cc3b43ea..0470d4f5 100644 --- a/hw/rtl/Vortex_Cluster.v +++ b/hw/rtl/Vortex_Cluster.v @@ -208,10 +208,10 @@ module Vortex_Cluster #( // Core Req (DRAM Fills/WB) To L2 Request .core_req_valid (l2c_core_req_valid), - .core_req_mem_read (l2c_core_req_mem_read), - .core_req_mem_write (l2c_core_req_mem_write), + .core_req_read (l2c_core_req_mem_read), + .core_req_write (l2c_core_req_mem_write), .core_req_addr (l2c_core_req_addr), - .core_req_writedata ({l2c_core_req_data}), + .core_req_data ({l2c_core_req_data}), .core_req_rd (0), .core_req_wb (l2c_core_req_wb), .core_req_warp_num (0), @@ -226,13 +226,13 @@ module Vortex_Cluster #( // Core Writeback .core_rsp_valid (l2c_wb), `IGNORE_WARNINGS_BEGIN - .core_rsp_req_rd (), - .core_rsp_req_wb (), + .core_rsp_read (), + .core_rsp_write (), .core_rsp_warp_num (), .core_rsp_pc (), `IGNORE_WARNINGS_END - .core_rsp_readdata ({l2c_wb_data}), - .core_rsp_address (l2c_wb_addr), + .core_rsp_data ({l2c_wb_data}), + .core_rsp_addr (l2c_wb_addr), // L2 Cache DRAM Fill response .dram_rsp_valid (dram_rsp_valid), diff --git a/hw/rtl/Vortex_Socket.v b/hw/rtl/Vortex_Socket.v index 37b775f3..bb0f230e 100644 --- a/hw/rtl/Vortex_Socket.v +++ b/hw/rtl/Vortex_Socket.v @@ -209,10 +209,10 @@ module Vortex_Socket ( // Core Req (DRAM Fills/WB) To L2 Request .core_req_valid (l3c_core_req_valid), - .core_req_mem_read (l3c_core_req_mem_read), - .core_req_mem_write (l3c_core_req_mem_write), + .core_req_read (l3c_core_req_mem_read), + .core_req_write (l3c_core_req_mem_write), .core_req_addr (l3c_core_req_addr), - .core_req_writedata ({l3c_core_req_data}), + .core_req_data ({l3c_core_req_data}), .core_req_rd (0), .core_req_wb (l3c_core_req_wb), .core_req_warp_num (0), @@ -227,13 +227,13 @@ module Vortex_Socket ( // Core Writeback .core_rsp_valid (l3c_wb), `IGNORE_WARNINGS_BEGIN - .core_rsp_req_rd (), - .core_rsp_req_wb (), + .core_rsp_read (), + .core_rsp_write (), .core_rsp_warp_num (), .core_rsp_pc (), `IGNORE_WARNINGS_END - .core_rsp_readdata ({l3c_wb_data}), - .core_rsp_address (l3c_wb_addr), + .core_rsp_data ({l3c_wb_data}), + .core_rsp_addr (l3c_wb_addr), // L2 Cache DRAM Fill response .dram_rsp_valid (dram_rsp_valid), diff --git a/hw/rtl/generic_cache/VX_cache.v b/hw/rtl/generic_cache/VX_cache.v index 67a1febb..0cd9096b 100644 --- a/hw/rtl/generic_cache/VX_cache.v +++ b/hw/rtl/generic_cache/VX_cache.v @@ -54,10 +54,10 @@ module VX_cache #( // Core request input wire [NUM_REQUESTS-1:0] core_req_valid, - input wire [NUM_REQUESTS-1:0][2:0] core_req_mem_read, - input wire [NUM_REQUESTS-1:0][2:0] core_req_mem_write, + input wire [NUM_REQUESTS-1:0][2:0] core_req_read, + input wire [NUM_REQUESTS-1:0][2:0] core_req_write, input wire [NUM_REQUESTS-1:0][31:0] core_req_addr, - input wire [NUM_REQUESTS-1:0][`WORD_SIZE_RNG] core_req_writedata, + input wire [NUM_REQUESTS-1:0][`WORD_SIZE_RNG] core_req_data, output wire core_req_ready, // Core request meta data @@ -69,10 +69,10 @@ module VX_cache #( // Core response output wire [NUM_REQUESTS-1:0] core_rsp_valid, - output wire [4:0] core_rsp_req_rd, - output wire [1:0] core_rsp_req_wb, - output wire [NUM_REQUESTS-1:0][31:0] core_rsp_address, - output wire [NUM_REQUESTS-1:0][`WORD_SIZE_RNG] core_rsp_readdata, + output wire [4:0] core_rsp_read, + output wire [1:0] core_rsp_write, + output wire [NUM_REQUESTS-1:0][31:0] core_rsp_addr, + output wire [NUM_REQUESTS-1:0][`WORD_SIZE_RNG] core_rsp_data, input wire core_rsp_ready, // Core response meta data @@ -230,11 +230,11 @@ module VX_cache #( .core_rsp_ready (core_rsp_ready), .core_rsp_valid (core_rsp_valid), - .core_rsp_req_rd (core_rsp_req_rd), - .core_rsp_req_wb (core_rsp_req_wb), + .core_rsp_read (core_rsp_read), + .core_rsp_write (core_rsp_write), .core_rsp_warp_num (core_rsp_warp_num), - .core_rsp_readdata (core_rsp_readdata), - .core_rsp_address (core_rsp_address), + .core_rsp_data (core_rsp_data), + .core_rsp_addr (core_rsp_addr), .core_rsp_pc (core_rsp_pc) ); @@ -303,13 +303,13 @@ module VX_cache #( // Core Req assign curr_bank_valids = per_bank_valids[curr_bank]; assign curr_bank_addr = core_req_addr; - assign curr_bank_writedata = core_req_writedata; + assign curr_bank_writedata = core_req_data; assign curr_bank_rd = core_req_rd; assign curr_bank_wb = core_req_wb; assign curr_bank_pc = core_req_pc; assign curr_bank_warp_num = core_req_warp_num; - assign curr_bank_mem_read = core_req_mem_read; - assign curr_bank_mem_write = core_req_mem_write; + assign curr_bank_mem_read = core_req_read; + assign curr_bank_mem_write = core_req_write; assign per_bank_reqq_full[curr_bank] = curr_bank_reqq_full; // Core WB diff --git a/hw/rtl/generic_cache/VX_cache_wb_sel_merge.v b/hw/rtl/generic_cache/VX_cache_wb_sel_merge.v index e029cc4a..968fa749 100644 --- a/hw/rtl/generic_cache/VX_cache_wb_sel_merge.v +++ b/hw/rtl/generic_cache/VX_cache_wb_sel_merge.v @@ -56,12 +56,12 @@ module VX_cache_wb_sel_merge #( // Core Writeback input wire core_rsp_ready, output reg [NUM_REQUESTS-1:0] core_rsp_valid, - output reg [NUM_REQUESTS-1:0][`WORD_SIZE_RNG] core_rsp_readdata, + output reg [NUM_REQUESTS-1:0][`WORD_SIZE_RNG] core_rsp_data, output reg [NUM_REQUESTS-1:0][31:0] core_rsp_pc, - output wire [4:0] core_rsp_req_rd, - output wire [1:0] core_rsp_req_wb, + output wire [4:0] core_rsp_read, + output wire [1:0] core_rsp_write, output wire [`NW_BITS-1:0] core_rsp_warp_num, - output reg [NUM_REQUESTS-1:0][31:0] core_rsp_address + output reg [NUM_REQUESTS-1:0][31:0] core_rsp_addr ); reg [NUM_BANKS-1:0] per_bank_wb_pop_unqual; @@ -86,17 +86,17 @@ module VX_cache_wb_sel_merge #( .found (found_bank) ); - assign core_rsp_req_rd = per_bank_wb_rd[main_bank_index]; - assign core_rsp_req_wb = per_bank_wb_wb[main_bank_index]; + assign core_rsp_read = per_bank_wb_rd[main_bank_index]; + assign core_rsp_write = per_bank_wb_wb[main_bank_index]; assign core_rsp_warp_num = per_bank_wb_warp_num[main_bank_index]; integer this_bank; generate always @(*) begin core_rsp_valid = 0; - core_rsp_readdata = 0; + core_rsp_data = 0; core_rsp_pc = 0; - core_rsp_address = 0; + core_rsp_addr = 0; for (this_bank = 0; this_bank < NUM_BANKS; this_bank = this_bank + 1) begin if ((FUNC_ID == `L2FUNC_ID) || (FUNC_ID == `L3FUNC_ID)) begin if (found_bank @@ -105,9 +105,9 @@ module VX_cache_wb_sel_merge #( && ((main_bank_index == `LOG2UP(NUM_BANKS)'(this_bank)) || (per_bank_wb_tid[this_bank] != per_bank_wb_tid[main_bank_index]))) begin core_rsp_valid[per_bank_wb_tid[this_bank]] = 1; - core_rsp_readdata[per_bank_wb_tid[this_bank]] = per_bank_wb_data[this_bank]; + core_rsp_data[per_bank_wb_tid[this_bank]] = per_bank_wb_data[this_bank]; core_rsp_pc[per_bank_wb_tid[this_bank]] = per_bank_wb_pc[this_bank]; - core_rsp_address[per_bank_wb_tid[this_bank]] = per_bank_wb_address[this_bank]; + core_rsp_addr[per_bank_wb_tid[this_bank]] = per_bank_wb_address[this_bank]; per_bank_wb_pop_unqual[this_bank] = 1; end else begin per_bank_wb_pop_unqual[this_bank] = 0; @@ -121,9 +121,9 @@ module VX_cache_wb_sel_merge #( && (per_bank_wb_rd[this_bank] == per_bank_wb_rd[main_bank_index]) && (per_bank_wb_warp_num[this_bank] == per_bank_wb_warp_num[main_bank_index])) begin core_rsp_valid[per_bank_wb_tid[this_bank]] = 1; - core_rsp_readdata[per_bank_wb_tid[this_bank]] = per_bank_wb_data[this_bank]; + core_rsp_data[per_bank_wb_tid[this_bank]] = per_bank_wb_data[this_bank]; core_rsp_pc[per_bank_wb_tid[this_bank]] = per_bank_wb_pc[this_bank]; - core_rsp_address[per_bank_wb_tid[this_bank]] = per_bank_wb_address[this_bank]; + core_rsp_addr[per_bank_wb_tid[this_bank]] = per_bank_wb_address[this_bank]; per_bank_wb_pop_unqual[this_bank] = 1; end else begin per_bank_wb_pop_unqual[this_bank] = 0; diff --git a/hw/rtl/interfaces/VX_gpu_dcache_req_if.v b/hw/rtl/interfaces/VX_gpu_dcache_req_if.v index 60c2befb..0bad6788 100644 --- a/hw/rtl/interfaces/VX_gpu_dcache_req_if.v +++ b/hw/rtl/interfaces/VX_gpu_dcache_req_if.v @@ -9,10 +9,10 @@ interface VX_gpu_dcache_req_if #( // Core request wire [NUM_REQUESTS-1:0] core_req_valid; - wire [NUM_REQUESTS-1:0][2:0] core_req_mem_read; - wire [NUM_REQUESTS-1:0][2:0] core_req_mem_write; + wire [NUM_REQUESTS-1:0][2:0] core_req_read; + wire [NUM_REQUESTS-1:0][2:0] core_req_write; wire [NUM_REQUESTS-1:0][31:0] core_req_addr; - wire [NUM_REQUESTS-1:0][31:0] core_req_writedata; + wire [NUM_REQUESTS-1:0][31:0] core_req_data; wire core_req_ready; // Core request Meta data diff --git a/hw/rtl/interfaces/VX_gpu_dcache_rsp_if.v b/hw/rtl/interfaces/VX_gpu_dcache_rsp_if.v index b7569072..7223c5c8 100644 --- a/hw/rtl/interfaces/VX_gpu_dcache_rsp_if.v +++ b/hw/rtl/interfaces/VX_gpu_dcache_rsp_if.v @@ -10,11 +10,11 @@ interface VX_gpu_dcache_rsp_if #( // Core response wire [NUM_REQUESTS-1:0] core_rsp_valid; `IGNORE_WARNINGS_BEGIN - wire [4:0] core_rsp_req_rd; - wire [1:0] core_rsp_req_wb; + wire [4:0] core_rsp_read; + wire [1:0] core_rsp_write; `IGNORE_WARNINGS_END - wire [NUM_REQUESTS-1:0][31:0] core_rsp_pc; - wire [NUM_REQUESTS-1:0][31:0] core_rsp_readdata; + //wire [NUM_REQUESTS-1:0][31:0] core_rsp_pc; + wire [NUM_REQUESTS-1:0][31:0] core_rsp_data; wire core_rsp_ready; // Core response meta data