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fix

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This commit is contained in:
felsabbagh3
2019-10-21 12:16:17 -04:00
parent ce49e2f223
commit 0672389edc
2 changed files with 11 additions and 8 deletions
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18
rtl/VX_scheduler.v
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@@ -4,6 +4,7 @@
module VX_scheduler (
input wire clk,
input wire reset,
input wire memory_delay,
VX_frE_to_bckE_req_inter VX_bckE_req,
VX_wb_inter VX_writeback_inter,
@@ -16,11 +17,6 @@ module VX_scheduler (
reg rename_table[31:0];
initial begin
integer i;
for (i = 0; i < 32; i = i + 1) rename_table[i] = 0;
end
wire valid_wb = (VX_writeback_inter.wb != 0) && (|VX_writeback_inter.wb_valid) && (VX_writeback_inter.rd != 0);
wire wb_inc = (VX_bckE_req.wb != 0) && (VX_bckE_req.rd != 0);
@@ -41,10 +37,16 @@ module VX_scheduler (
assign schedule_delay = (rename_valid) && (|VX_bckE_req.valid) || memory_delay;
integer i;
always @(posedge clk) begin
if (valid_wb ) rename_table[VX_writeback_inter.rd] <= 0;
if (!schedule_delay && wb_inc) rename_table[VX_bckE_req.rd] <= 1;
always @(posedge clk or posedge reset) begin
if (reset) begin
for (i = 0; i < 32; i = i + 1) rename_table[i] = 0;
end else begin
if (valid_wb ) rename_table[VX_writeback_inter.rd] <= 0;
if (!schedule_delay && wb_inc) rename_table[VX_bckE_req.rd] <= 1;
end
end

1
rtl/Vortex.v
View File

@@ -76,6 +76,7 @@ VX_front_end vx_front_end(
VX_scheduler schedule(
.clk (clk),
.reset (reset),
.memory_delay (memory_delay),
.VX_bckE_req (VX_bckE_req),
.VX_writeback_inter(VX_writeback_inter),