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minor update

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This commit is contained in:
Blaise Tine
2021-04-01 12:34:18 -07:00
parent a194521683
commit 04a96e89c9
3 changed files with 10 additions and 9 deletions
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11
hw/rtl/VX_lsu_unit.v
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@@ -121,10 +121,13 @@ module VX_lsu_unit #(
|| (req_is_dup & dcache_req_if.ready[0]); || (req_is_dup & dcache_req_if.ready[0]);
always @(posedge clk) begin always @(posedge clk) begin
if (reset || sent_all_ready) begin if (reset) begin
req_sent_mask <= 0; req_sent_mask <= 0;
end else begin end else begin
req_sent_mask <= req_sent_mask | dcache_req_fire; if (sent_all_ready)
req_sent_mask <= 0;
else
req_sent_mask <= req_sent_mask | dcache_req_fire;
end end
end end
@@ -228,8 +231,8 @@ module VX_lsu_unit #(
case (`LSU_FMT(rsp_type)) case (`LSU_FMT(rsp_type))
`FMT_B: rsp_data[i] = 32'(signed'(rsp_data_shifted[7:0])); `FMT_B: rsp_data[i] = 32'(signed'(rsp_data_shifted[7:0]));
`FMT_H: rsp_data[i] = 32'(signed'(rsp_data_shifted[15:0])); `FMT_H: rsp_data[i] = 32'(signed'(rsp_data_shifted[15:0]));
`FMT_BU: rsp_data[i] = 32'(rsp_data_shifted[7:0]); `FMT_BU: rsp_data[i] = 32'(unsigned'(rsp_data_shifted[7:0]));
`FMT_HU: rsp_data[i] = 32'(rsp_data_shifted[15:0]); `FMT_HU: rsp_data[i] = 32'(unsigned'(rsp_data_shifted[15:0]));
default: rsp_data[i] = rsp_data_shifted; default: rsp_data[i] = rsp_data_shifted;
endcase endcase
end end

3
hw/rtl/cache/VX_cache.v vendored
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@@ -168,8 +168,7 @@ module VX_cache #(
.NUM_BANKS (NUM_BANKS) .NUM_BANKS (NUM_BANKS)
) flush_ctrl ( ) flush_ctrl (
.clk (clk), .clk (clk),
.reset (reset), .reset (reset || flush),
.flush (flush),
.addr_out (flush_addr), .addr_out (flush_addr),
.valid_out (flush_enable) .valid_out (flush_enable)
); );

5
hw/rtl/cache/VX_flush_ctrl.v vendored
View File

@@ -9,8 +9,7 @@ module VX_flush_ctrl #(
parameter NUM_BANKS = 1 parameter NUM_BANKS = 1
) ( ) (
input wire clk, input wire clk,
input wire reset, input wire reset,
input wire flush,
output wire [`LINE_SELECT_BITS-1:0] addr_out, output wire [`LINE_SELECT_BITS-1:0] addr_out,
output wire valid_out output wire valid_out
); );
@@ -18,7 +17,7 @@ module VX_flush_ctrl #(
reg [`LINE_SELECT_BITS-1:0] flush_ctr; reg [`LINE_SELECT_BITS-1:0] flush_ctr;
always @(posedge clk) begin always @(posedge clk) begin
if (reset || flush) begin if (reset) begin
flush_enable <= 1; flush_enable <= 1;
flush_ctr <= 0; flush_ctr <= 0;
end else begin end else begin