diff --git a/hw/rtl/VX_lsu_unit.v b/hw/rtl/VX_lsu_unit.v
index d4960ded..20aaef69 100644
--- a/hw/rtl/VX_lsu_unit.v
+++ b/hw/rtl/VX_lsu_unit.v
@@ -121,10 +121,13 @@ module VX_lsu_unit #(
                          || (req_is_dup & dcache_req_if.ready[0]);
 
     always @(posedge clk) begin
-        if (reset || sent_all_ready) begin
+        if (reset) begin
             req_sent_mask <= 0;
         end else begin
-            req_sent_mask <= req_sent_mask | dcache_req_fire;            
+            if (sent_all_ready)
+                req_sent_mask <= 0;
+            else
+                req_sent_mask <= req_sent_mask | dcache_req_fire;            
         end
     end
 
@@ -228,8 +231,8 @@ module VX_lsu_unit #(
             case (`LSU_FMT(rsp_type))
             `FMT_B:  rsp_data[i] = 32'(signed'(rsp_data_shifted[7:0]));
             `FMT_H:  rsp_data[i] = 32'(signed'(rsp_data_shifted[15:0]));
-            `FMT_BU: rsp_data[i] = 32'(rsp_data_shifted[7:0]);
-            `FMT_HU: rsp_data[i] = 32'(rsp_data_shifted[15:0]);
+            `FMT_BU: rsp_data[i] = 32'(unsigned'(rsp_data_shifted[7:0]));
+            `FMT_HU: rsp_data[i] = 32'(unsigned'(rsp_data_shifted[15:0]));
             default: rsp_data[i] = rsp_data_shifted;     
             endcase
         end        
diff --git a/hw/rtl/cache/VX_cache.v b/hw/rtl/cache/VX_cache.v
index 63133664..f0bf1d9d 100644
--- a/hw/rtl/cache/VX_cache.v
+++ b/hw/rtl/cache/VX_cache.v
@@ -168,8 +168,7 @@ module VX_cache #(
         .NUM_BANKS  (NUM_BANKS)
     ) flush_ctrl (
         .clk       (clk),
-        .reset     (reset),
-        .flush     (flush),        
+        .reset     (reset || flush),
         .addr_out  (flush_addr),
         .valid_out (flush_enable)
     );
diff --git a/hw/rtl/cache/VX_flush_ctrl.v b/hw/rtl/cache/VX_flush_ctrl.v
index 261197b6..d9b7ca9d 100644
--- a/hw/rtl/cache/VX_flush_ctrl.v
+++ b/hw/rtl/cache/VX_flush_ctrl.v
@@ -9,8 +9,7 @@ module VX_flush_ctrl #(
     parameter NUM_BANKS         = 1
 ) (
     input wire  clk,
-    input wire  reset,
-    input wire  flush,    
+    input wire  reset,    
     output wire [`LINE_SELECT_BITS-1:0] addr_out,
     output wire valid_out
 );
@@ -18,7 +17,7 @@ module VX_flush_ctrl #(
     reg [`LINE_SELECT_BITS-1:0] flush_ctr;
 
     always @(posedge clk) begin
-        if (reset || flush) begin
+        if (reset) begin
             flush_enable <= 1;
             flush_ctr    <= 0;
         end else begin