-T.K.-
|
e078fcba49
|
REFACTOR: rename arty35t explicitly
|
2023-12-04 01:54:59 -08:00 |
|
Jerry Zhao
|
a5597fd32f
|
Support using HarnessBinders without IOBinders
|
2023-10-25 11:49:16 -07:00 |
|
Jerry Zhao
|
5495d05aa0
|
Bump to latest rocket-chip
|
2023-08-22 11:28:57 -07:00 |
|
Jerry Zhao
|
2077e4304d
|
Explicitly provide refClockFreqMHz to harnessClockInstantiator
|
2023-05-13 11:18:03 -07:00 |
|
Jerry Zhao
|
b8e95e0305
|
Rename implicit clock/reset to referenceclock/reset
|
2023-05-12 15:11:44 -07:00 |
|
Jerry Zhao
|
607c2b5a73
|
Unify multi-node btw chipyard/firechip | unify harness clocking
|
2023-05-12 08:41:34 -07:00 |
|
Jerry Zhao
|
64ad77bbcf
|
Make FPGA flows use the harnessClockInstantiator
|
2023-05-11 15:04:04 -07:00 |
|
Jerry Zhao
|
ac281daa78
|
Move TestHarness to chipyard.harness, make chipyard/harness directory
|
2023-05-08 08:00:56 -07:00 |
|
Jerry Zhao
|
df2e5ad9dc
|
Bump to latest rocket-chip/chisel3.5.6
|
2023-03-28 16:48:27 -07:00 |
|
abejgonzalez
|
292cc753ce
|
Run pre-commit on all files
|
2022-12-21 15:59:46 -08:00 |
|
-T.K.-
|
1b7457d2fc
|
FIX: fix Arty FPGA reset signal (#1257)
|
2022-12-07 19:34:35 -08:00 |
|
Jerry Zhao
|
f668ffdb03
|
Switch PRCI to HarnessBinder/IOBinders
|
2021-09-29 11:39:52 -07:00 |
|
abejgonzalez
|
09ef82cabf
|
Update harnessClk/Rst naming to buildtop | Small docs cleanup
|
2021-03-22 13:11:12 -07:00 |
|
abejgonzalez
|
a281869041
|
Fix Arty merge and errors from CY bump
|
2020-11-05 15:04:44 -08:00 |
|
abejgonzalez
|
a7ab0dab59
|
Updated VCU118 | Bumped naming on Arty
|
2020-11-05 13:59:10 -08:00 |
|
abejgonzalez
|
3994bcecdf
|
Merge remote-tracking branch 'secret/local-fpga-arty-harnessbinders' into local-fpga-support
|
2020-11-05 11:08:36 -08:00 |
|
abejgonzalez
|
dda7622c29
|
temp commit
|
2020-10-14 14:49:22 -07:00 |
|
James Dunn
|
dca56cd858
|
Removing redefinitions of HasHarnessSignalReferences and HasTestHarnessFunctions in TestHarness.scala.
|
2020-10-10 19:55:02 -07:00 |
|
dunn
|
252f9c6a12
|
Beginning to modify Arty TestHarness to conform with HarnessBinders. Currently does not compile; debugging.
|
2020-10-07 11:55:16 -07:00 |
|
James Dunn
|
9135cda959
|
Bypassing AON for system.reset. Using reset_core in ArtyShell test harness, which is derived from Xilinx reset IP block's mb_reset. Changing dutReset to same reset_core.
|
2020-09-17 13:43:28 -07:00 |
|
abejgonzalez
|
a8083aa570
|
First pass at fpga-shells with IOBinders
|
2020-09-07 11:48:27 -07:00 |
|