270 lines
11 KiB
Scala
270 lines
11 KiB
Scala
package chipyard
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import org.chipsalliance.cde.config.{Config}
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import freechips.rocketchip.diplomacy.{AsynchronousCrossing}
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import freechips.rocketchip.subsystem.{SBUS, MBUS}
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import constellation.channel._
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import constellation.routing._
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import constellation.router._
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import constellation.topology._
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import constellation.noc._
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import constellation.soc.{GlobalNoCParams}
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import scala.collection.immutable.ListMap
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/*
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* This config demonstrates a SoC architecture with three different
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* independent interconnects. The SBus interconnect is the main
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* backbone, handling core traffic to the L2s and peripherals.
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* The MBus handles requests to the DRAM and external memory.
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* The CBus handles requests to control devices.
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*
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* Topologies:
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*
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* 12 - 13 - 14 - 15
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* | | | |
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* 8 -- 9 - 10 - 11 0 -- 1 -- 2 -- 3
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* | | | | | |
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* 4 -- 5 -- 6 -- 7 7 -- 6 -- 5 -- 4
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* | | | |
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* 0 -- 1 -- 2 -- 3
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*
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* This table describes the mappings of each edge onto the network
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*
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* SI/SO: Inward/outward names into sbus
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* MI/MO: Inward/outward names into mbus
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*
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* |(12)__________|(13)__________|(14)__________|(15)__________|
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* | | Core 6 | Core 7 | |
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* | | SI:Core 6 | SI:Core 7 | |
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* |(8)___________|(9)___________|(10)__________|(11)__________|
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* | Core 4 | L2 2 | L2 3 | Core 5 |
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* | SI:Core 4 | S0:system[2] | SO:system[3] | SI:Core 5 |
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* |(4)___________|(5)___________|(6)___________|(7)___________|
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* | Core 2 | L2 0 | L2 1 | Core 3 |
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* | SI:Core 2 | SO:system[0] | SO:system[1] | SI:Core 3 |
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* |(0)___________|(1)___________|(2)___________|(3)___________|
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* | FBus | Core 0 | Core 1 | Pbus |
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* | SI:serial_tl | SI:Core 0 | SI:Core 1 | SO:pbus |
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* |______________|______________|______________|______________|
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*
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* |(0)___________|(1)___________|(2)___________|(3)___________|
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* | DRAM 0 | L2 0 | L2 1 | DRAM 1 |
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* | M0:system[0] | MI:L2[0] | MI:L2[1] | M0:system[1] |
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* | M0:serdesser | | | |
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* |______________|______________|______________|______________|
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* |||||||||||||| ||||||||||||||
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* |(7)___________|(6)___________|(5)___________|(4)___________|
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* | DRAM 2 | L2 2 | L2 3 | DRAM 3 |
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* | M0:system[2] | MI:L2[2] | MI:L2[3] | M0:system[3] |
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* | | | | |
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* |______________|______________|______________|______________|
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*/
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// DOC include start: MultiNoCConfig
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class MultiNoCConfig extends Config(
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new constellation.soc.WithCbusNoC(constellation.protocol.SimpleTLNoCParams(
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constellation.protocol.DiplomaticNetworkNodeMapping(
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inNodeMapping = ListMap(
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"serial_tl" -> 0),
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outNodeMapping = ListMap(
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"error" -> 1, "ctrls[0]" -> 2, "pbus" -> 3, "plic" -> 4,
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"clint" -> 5, "dmInner" -> 6, "bootrom" -> 7, "clock" -> 8)),
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NoCParams(
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topology = TerminalRouter(BidirectionalLine(9)),
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channelParamGen = (a, b) => UserChannelParams(Seq.fill(5) { UserVirtualChannelParams(4) }),
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routingRelation = NonblockingVirtualSubnetworksRouting(TerminalRouterRouting(BidirectionalLineRouting()), 5, 1))
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)) ++
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new constellation.soc.WithMbusNoC(constellation.protocol.SimpleTLNoCParams(
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constellation.protocol.DiplomaticNetworkNodeMapping(
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inNodeMapping = ListMap(
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"L2 InclusiveCache[0]" -> 1, "L2 InclusiveCache[1]" -> 2,
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"L2 InclusiveCache[2]" -> 5, "L2 InclusiveCache[3]" -> 6),
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outNodeMapping = ListMap(
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"system[0]" -> 0, "system[1]" -> 3, "system[2]" -> 4 , "system[3]" -> 7,
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"serial_tl_0" -> 0)),
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NoCParams(
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topology = TerminalRouter(BidirectionalTorus1D(8)),
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channelParamGen = (a, b) => UserChannelParams(Seq.fill(10) { UserVirtualChannelParams(4) }),
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routingRelation = BlockingVirtualSubnetworksRouting(TerminalRouterRouting(BidirectionalTorus1DShortestRouting()), 5, 2))
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)) ++
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new constellation.soc.WithSbusNoC(constellation.protocol.SimpleTLNoCParams(
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constellation.protocol.DiplomaticNetworkNodeMapping(
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inNodeMapping = ListMap(
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"Core 0" -> 1, "Core 1" -> 2, "Core 2" -> 4 , "Core 3" -> 7,
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"Core 4" -> 8, "Core 5" -> 11, "Core 6" -> 13, "Core 7" -> 14,
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"serial_tl" -> 0),
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outNodeMapping = ListMap(
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"system[0]" -> 5, "system[1]" -> 6, "system[2]" -> 9, "system[3]" -> 10,
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"pbus" -> 3)),
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NoCParams(
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topology = TerminalRouter(Mesh2D(4, 4)),
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channelParamGen = (a, b) => UserChannelParams(Seq.fill(8) { UserVirtualChannelParams(4) }),
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routingRelation = BlockingVirtualSubnetworksRouting(TerminalRouterRouting(Mesh2DEscapeRouting()), 5, 1))
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)) ++
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new freechips.rocketchip.subsystem.WithNBigCores(8) ++
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new freechips.rocketchip.subsystem.WithNBanks(4) ++
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new freechips.rocketchip.subsystem.WithNMemoryChannels(4) ++
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new chipyard.config.AbstractConfig
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)
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// DOC include end: MultiNoCConfig
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/*
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* 10 - 11 - 12 - 13 - 14
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* |
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* 0 --- 1 --- 2 --- 3
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* | |
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* 9 4
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* | |
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* 8 --- 7 --- 6 --- 5
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* |
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* 15 - 16 - 17 - 18 - 19
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*
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* SI/SO: Inward/outward names into sbus
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* MI/MO: Inward/outward names into mbus
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*
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* Agent | Bus | String | node
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* ================================
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* Core 0 | SI | Core 0 | 2
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* Core 1 | SI | Core 1 | 10
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* Core 2 | SI | Core 2 | 11
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* Core 3 | SI | Core 3 | 13
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* Core 4 | SI | Core 4 | 14
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* Core 5 | SI | Core 5 | 15
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* Core 6 | SI | Core 6 | 16
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* Core 7 | SI | Core 7 | 18
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* Core 8 | SI | Core 8 | 19
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* fbus | SI | serial_tl | 9
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* pbus | SO | pbus | 4
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* L2 0 | SO | system[0] | 0
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* L2 1 | SO | system[1] | 2
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* L2 2 | SO | system[2] | 8
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* L2 3 | SO | system[3] | 6
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* L2 0 | MI | Cache[0] | 0
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* L2 1 | MI | Cache[1] | 2
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* L2 2 | MI | Cache[2] | 8
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* L2 3 | MI | Cache[3] | 6
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* DRAM 0 | MO | system[0] | 3
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* DRAM 1 | MO | system[1] | 5
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* spad | MO | ram[0] | 9
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*/
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// DOC include start: SharedNoCConfig
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class SharedNoCConfig extends Config(
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new constellation.soc.WithGlobalNoC(GlobalNoCParams(
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NoCParams(
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topology = TerminalRouter(HierarchicalTopology(
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base = UnidirectionalTorus1D(10),
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children = Seq(HierarchicalSubTopology(1, 2, BidirectionalLine(5)),
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HierarchicalSubTopology(7, 2, BidirectionalLine(5))))),
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channelParamGen = (a, b) => UserChannelParams(Seq.fill(22) { UserVirtualChannelParams(4) }),
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routingRelation = NonblockingVirtualSubnetworksRouting(TerminalRouterRouting(HierarchicalRouting(
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baseRouting = UnidirectionalTorus1DDatelineRouting(),
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childRouting = Seq(BidirectionalLineRouting(),
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BidirectionalLineRouting()))), 10, 2)
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)
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)) ++
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new constellation.soc.WithMbusNoC(constellation.protocol.GlobalTLNoCParams(
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constellation.protocol.DiplomaticNetworkNodeMapping(
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inNodeMapping = ListMap(
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"Cache[0]" -> 0, "Cache[1]" -> 2, "Cache[2]" -> 8, "Cache[3]" -> 6),
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outNodeMapping = ListMap(
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"system[0]" -> 3, "system[1]" -> 5,
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"ram[0]" -> 9))
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)) ++
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new constellation.soc.WithSbusNoC(constellation.protocol.GlobalTLNoCParams(
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constellation.protocol.DiplomaticNetworkNodeMapping(
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inNodeMapping = ListMap(
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"serial_tl" -> 9, "Core 0" -> 2,
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"Core 1" -> 10, "Core 2" -> 11, "Core 3" -> 13, "Core 4" -> 14,
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"Core 5" -> 15, "Core 6" -> 16, "Core 7" -> 18, "Core 8" -> 19),
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outNodeMapping = ListMap(
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"system[0]" -> 0, "system[1]" -> 2, "system[2]" -> 8, "system[3]" -> 6,
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"pbus" -> 4))
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)) ++
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new freechips.rocketchip.subsystem.WithNBigCores(8) ++
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new freechips.rocketchip.subsystem.WithNBanks(4) ++
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new freechips.rocketchip.subsystem.WithNMemoryChannels(2) ++
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new chipyard.config.AbstractConfig
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)
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// DOC include end: SharedNoCConfig
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// This Config implements a simple ring interconnect for the system bus
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class SbusRingNoCConfig extends Config(
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new constellation.soc.WithSbusNoC(constellation.protocol.SplitACDxBETLNoCParams(
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constellation.protocol.DiplomaticNetworkNodeMapping(
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inNodeMapping = ListMap(
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"Core 0" -> 0,
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"Core 1" -> 1,
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"Core 2" -> 2,
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"Core 3" -> 3,
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"Core 4" -> 4,
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"Core 5" -> 5,
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"Core 6" -> 6,
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"Core 7" -> 7,
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"serial_tl" -> 8),
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outNodeMapping = ListMap(
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"system[0]" -> 9,
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"system[1]" -> 10,
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"system[2]" -> 11,
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"system[3]" -> 12,
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"pbus" -> 8)), // TSI is on the pbus, so serial-tl and pbus should be on the same node
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acdNoCParams = NoCParams(
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topology = UnidirectionalTorus1D(13),
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channelParamGen = (a, b) => UserChannelParams(Seq.fill(6) { UserVirtualChannelParams(4) }),
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routingRelation = NonblockingVirtualSubnetworksRouting(UnidirectionalTorus1DDatelineRouting(), 3, 2)),
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beNoCParams = NoCParams(
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topology = UnidirectionalTorus1D(13),
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channelParamGen = (a, b) => UserChannelParams(Seq.fill(4) { UserVirtualChannelParams(1) }),
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routingRelation = NonblockingVirtualSubnetworksRouting(UnidirectionalTorus1DDatelineRouting(), 2, 2))
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)) ++
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new freechips.rocketchip.subsystem.WithNBigCores(8) ++
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new freechips.rocketchip.subsystem.WithNBanks(4) ++
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new chipyard.config.AbstractConfig
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)
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// This config integrates a mesh interconnect for the system bus, and divides the system bus
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// tilelink messages across two isolated interconnects
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class SbusMeshNoCConfig extends Config(
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new constellation.soc.WithSbusNoC(constellation.protocol.SplitACDxBETLNoCParams(
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constellation.protocol.DiplomaticNetworkNodeMapping(
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inNodeMapping = ListMap(
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"Core 0 " -> 0,
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"Core 1 " -> 1,
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"Core 2 " -> 2,
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"Core 3 " -> 3,
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"Core 4 " -> 4,
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"Core 5 " -> 7,
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"Core 6 " -> 8,
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"Core 7 " -> 11,
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"Core 8 " -> 12,
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"Core 9 " -> 13,
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"Core 10 " -> 14,
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"Core 11 " -> 15,
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"serial_tl" -> 0),
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outNodeMapping = ListMap(
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"system[0]" -> 5,
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"system[1]" -> 6,
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"system[2]" -> 9,
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"system[3]" -> 10,
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"pbus" -> 0)), // TSI is on the pbus, so serial-tl and pbus should be on the same node
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acdNoCParams = NoCParams(
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topology = Mesh2D(4, 4),
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channelParamGen = (a, b) => UserChannelParams(Seq.fill(3) { UserVirtualChannelParams(3) }, unifiedBuffer = false),
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routerParams = (i) => UserRouterParams(combineRCVA=true, combineSAST=true),
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routingRelation = NonblockingVirtualSubnetworksRouting(Mesh2DDimensionOrderedRouting(), 3, 1),
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),
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beNoCParams = NoCParams(
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topology = Mesh2D(4, 4),
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channelParamGen = (a, b) => UserChannelParams(Seq.fill(2) { UserVirtualChannelParams(3) }, unifiedBuffer = false),
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routerParams = (i) => UserRouterParams(combineRCVA=true, combineSAST=true),
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routingRelation = NonblockingVirtualSubnetworksRouting(Mesh2DDimensionOrderedRouting(), 2, 1),
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),
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beDivision = 4
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), inlineNoC = true) ++
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new freechips.rocketchip.subsystem.WithNBigCores(12) ++
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new freechips.rocketchip.subsystem.WithNBanks(4) ++
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new chipyard.config.WithSystemBusWidth(128) ++
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new chipyard.config.AbstractConfig
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)
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