43f6083b69
Cores now have an extra CoreParam, useSupervisor which was set to the default false. Whether a core has supervisor mode is the union of this and useVM which defaults true so not change was made by this addition. BusTopologies are now set with the Config system rather than a system mixin and so all configs now include the config most similar to the previous mixin Testchipip was updated to be able to replace the systembus, in this new config system, with a ring bus. The L2 cache repo needed a similar update on how to find the buses. It currently points to the ucb-bar fork Treadle is bumped to its release branch
43 lines
2.4 KiB
Scala
43 lines
2.4 KiB
Scala
package chipyard
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import chisel3._
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import freechips.rocketchip.config.{Config}
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// ---------------------
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// Ariane Configs
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// ---------------------
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class ArianeConfig extends Config(
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new chipyard.iobinders.WithUARTAdapter ++ // display UART with a SimUARTAdapter
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new chipyard.iobinders.WithTieOffInterrupts ++ // tie off top-level interrupts
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new chipyard.iobinders.WithSimAXIMem ++ // drive the master AXI4 memory with a SimAXIMem
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new chipyard.iobinders.WithTiedOffDebug ++ // tie off debug (since we are using SimSerial for testing)
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new chipyard.iobinders.WithSimSerial ++ // drive TSI with SimSerial for testing
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new testchipip.WithTSI ++ // use testchipip serial offchip link
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new chipyard.config.WithBootROM ++ // use default bootrom
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new chipyard.config.WithUART ++ // add a UART
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new freechips.rocketchip.subsystem.WithNoMMIOPort ++ // no top-level MMIO master port (overrides default set in rocketchip)
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new freechips.rocketchip.subsystem.WithNoSlavePort ++ // no top-level MMIO slave port (overrides default set in rocketchip)
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new freechips.rocketchip.subsystem.WithInclusiveCache ++ // use Sifive L2 cache
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new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++ // no external interrupts
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new ariane.WithNArianeCores(1) ++ // single Ariane core
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new freechips.rocketchip.subsystem.WithCoherentBusTopology ++ // hierarchical buses including mbus+l2
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new freechips.rocketchip.system.BaseConfig) // "base" rocketchip system
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class dmiArianeConfig extends Config(
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new chipyard.iobinders.WithUARTAdapter ++
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new chipyard.iobinders.WithTieOffInterrupts ++
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new chipyard.iobinders.WithSimAXIMem ++
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new chipyard.iobinders.WithTiedOffSerial ++
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new chipyard.iobinders.WithSimDebug ++ // add SimDebug and use it to drive simulation
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new chipyard.config.WithBootROM ++
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new chipyard.config.WithUART ++
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new freechips.rocketchip.subsystem.WithNoMMIOPort ++
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new freechips.rocketchip.subsystem.WithNoSlavePort ++
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new freechips.rocketchip.subsystem.WithInclusiveCache ++
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new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++
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new ariane.WithNArianeCores(1) ++
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new freechips.rocketchip.subsystem.WithCoherentBusTopology ++
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new freechips.rocketchip.system.BaseConfig)
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