28 lines
1.5 KiB
Markdown
28 lines
1.5 KiB
Markdown
# REBAR Framework [](https://circleci.com/gh/ucb-bar/project-template/tree/master)
|
|
|
|
## Using REBAR
|
|
|
|
To get started using REBAR, see the documentation on the REBAR documentation site: https://bar-project-template.readthedocs.io/en/latest/
|
|
|
|
## What is REBAR
|
|
|
|
REBAR is an open source starter template for your custom Chisel project.
|
|
It will allow you to leverage the Chisel HDL, Rocket Chip SoC generator, and other [Berkeley][berkeley] projects to produce a [RISC-V][riscv] SoC with everything from MMIO-mapped peripherals to custom accelerators.
|
|
It contains processor cores ([Rocket][rocket-chip], [BOOM][boom]), accelerators ([Hwacha][hwacha]), FPGA simulation tools ([FireSim][firesim]), ASIC tools ([HAMMER][hammer]) and other tooling to help create a full featured SoC.
|
|
REBAR is actively developed in the [Berkeley Architecture Research Group][ucb-bar] in the [Electrical Engineering and Computer Sciences Department][eecs] at the [University of California, Berkeley][berkeley].
|
|
|
|
## Resources
|
|
|
|
* REBAR Website: ...TBD at a later date...
|
|
* REBAR Documentation: https://bar-project-template.readthedocs.io/
|
|
|
|
[hwacha]:http://hwacha.org
|
|
[hammer]:https://github.com/ucb-bar/hammer
|
|
[firesim]:https://fires.im
|
|
[ucb-bar]: http://bar.eecs.berkeley.edu
|
|
[eecs]: https://eecs.berkeley.edu
|
|
[berkeley]: https://berkeley.edu
|
|
[riscv]: https://riscv.org/
|
|
[rocket-chip]: https://github.com/freechipsproject/rocket-chip
|
|
[boom]: https://github.com/ucb-bar/riscv-boom
|