Donggyu Kim aeb303a61b Colin's fixes

2017-10-03 11:56:30 -07:00

..

.clkgen

Moved clkgen -> .clkgen and pads -> .pads

2017-09-06 14:44:09 -07:00

.pads

Moved clkgen -> .clkgen and pads -> .pads

2017-09-06 14:44:09 -07:00

macros

Colin's fixes

2017-10-03 11:56:30 -07:00

retime

Added retime annotation

2017-09-06 14:44:09 -07:00

utils

DiGraph was being being confused with the DigGraph in firrtl. This led to pathological exceptions (#22)

2017-04-04 10:47:59 -07:00

ConvertToExtModPass.scala

Refactor repo for lastest changes to firrtl transform api changes (#19)

2017-04-02 04:10:46 -07:00

EnumerateModules.scala

Refactor repo for lastest changes to firrtl transform api changes (#19)

2017-04-02 04:10:46 -07:00

Generate.scala

Revert "[stevo]: add custom analog annotation" (#21)

2017-04-02 13:12:51 -07:00

RemoveUnusedModules.scala

Refactor repo for lastest changes to firrtl transform api changes (#19)

2017-04-02 04:10:46 -07:00

RenameModulesAndInstances.scala

Refactor repo for lastest changes to firrtl transform api changes (#19)

2017-04-02 04:10:46 -07:00

ReParentCircuit.scala

Refactor repo for lastest changes to firrtl transform api changes (#19)

2017-04-02 04:10:46 -07:00

ResetInverter.scala

Refactor repo for lastest changes to firrtl transform api changes (#19)

2017-04-02 04:10:46 -07:00