[
  {
    "type": "sram",
    "name": "tag_array_ext",
    "depth": 64,
    "width": 80,
    "ports": [
      {
        "clock port name": "RW0_clk",
        "mask granularity": 20,
        "output port name": "RW0_rdata",
        "input port name": "RW0_wdata",
        "address port name": "RW0_addr",
        "mask port name": "RW0_wmask",
        "chip enable port name": "RW0_en",
        "write enable port name": "RW0_wmode"
      }
    ]
  },
  {
    "type": "sram",
    "name": "T_1090_ext",
    "depth": 512,
    "width": 64,
    "ports": [
      {
        "clock port name": "RW0_clk",
        "output port name": "RW0_rdata",
        "input port name": "RW0_wdata",
        "address port name": "RW0_addr",
        "chip enable port name": "RW0_en",
        "write enable port name": "RW0_wmode"
      }
    ]
  },
  {
    "type": "sram",
    "name": "T_406_ext",
    "depth": 512,
    "width": 64,
    "ports": [
      {
        "clock port name": "RW0_clk",
        "mask granularity": 8,
        "output port name": "RW0_rdata",
        "input port name": "RW0_wdata",
        "address port name": "RW0_addr",
        "mask port name": "RW0_wmask",
        "chip enable port name": "RW0_en",
        "write enable port name": "RW0_wmode"
      }
    ]
  },
  {
    "type": "sram",
    "name": "T_2172_ext",
    "depth": 64,
    "width": 88,
    "ports": [
      {
        "clock port name": "W0_clk",
        "mask granularity": 22,
        "input port name": "W0_data",
        "address port name": "W0_addr",
        "chip enable port name": "W0_en",
        "mask port name": "W0_mask"
      },
      {
        "clock port name": "R0_clk",
        "output port name": "R0_data",
        "address port name": "R0_addr",
        "chip enable port name": "R0_en"
      }
    ]
  }
]