43f6083b69
Cores now have an extra CoreParam, useSupervisor which was set to the default false. Whether a core has supervisor mode is the union of this and useVM which defaults true so not change was made by this addition. BusTopologies are now set with the Config system rather than a system mixin and so all configs now include the config most similar to the previous mixin Testchipip was updated to be able to replace the systembus, in this new config system, with a ring bus. The L2 cache repo needed a similar update on how to find the buses. It currently points to the ucb-bar fork Treadle is bumped to its release branch
51 lines
1.5 KiB
Scala
51 lines
1.5 KiB
Scala
package tracegen
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import chisel3._
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import freechips.rocketchip.config.{Field, Parameters}
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import freechips.rocketchip.diplomacy.{LazyModule, LazyModuleImp, BufferParams}
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import freechips.rocketchip.groundtest.{DebugCombiner, TraceGenParams}
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import freechips.rocketchip.subsystem._
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case object BoomTraceGenKey extends Field[Seq[TraceGenParams]](Nil)
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case object TraceGenKey extends Field[Seq[TraceGenParams]](Nil)
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trait HasTraceGenTiles { this: BaseSubsystem =>
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val rocket_tiles = p(TraceGenKey).zipWithIndex.map { case (params, i) =>
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LazyModule(new TraceGenTile(i, params, p))
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}
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val boom_tiles = p(BoomTraceGenKey).zipWithIndex.map { case (params, i) =>
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LazyModule(new BoomTraceGenTile(i, params, p))
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}
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val tiles = rocket_tiles ++ boom_tiles
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tiles.foreach { t =>
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sbus.fromTile(None, buffer = BufferParams.default) { t.masterNode }
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}
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}
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trait HasTraceGenTilesModuleImp extends LazyModuleImp {
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val outer: HasTraceGenTiles
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val success = IO(Output(Bool()))
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outer.tiles.zipWithIndex.map { case(t, i) =>
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t.module.constants.hartid := i.U
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}
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val status = DebugCombiner(
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outer.rocket_tiles.map(_.module.status) ++
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outer.boom_tiles.map(_.module.status)
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)
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success := status.finished
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}
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class TraceGenSystem(implicit p: Parameters) extends BaseSubsystem
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with HasTraceGenTiles
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with CanHaveMasterAXI4MemPort {
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override lazy val module = new TraceGenSystemModuleImp(this)
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}
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class TraceGenSystemModuleImp(outer: TraceGenSystem)
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extends BaseSubsystemModuleImp(outer)
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with HasTraceGenTilesModuleImp
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