wu-arch/chipyard
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f77f1edecc1d0d28c8a071ac9a16872ca4861f25
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5 Commits

Author SHA1 Message Date
Hansung Kim
f77f1edecc Add fpnew packages and include dirs to vcs flags 
This is necessary because Verilog package definitions need to be compiled before
the modules that reference them, but the compilation order is not enforced with
addResource()s.
 2024-04-15 15:31:10 -07:00
Hansung Kim
3190224cfe Squelch inout coerce lint messages from vortex RTL 2024-01-16 16:32:30 -08:00
Jerry Zhao
4da1dea50f Support multi-binary-run in RTL sim 2023-05-24 16:48:18 -07:00
Jerry Zhao
a0569208a5 Fix VCS waveforms 2023-05-10 15:49:59 -07:00
abejgonzalez
95349755b5 Support TestDriver.v as top 2023-03-13 11:11:23 -07:00