 David Biancolin
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ebfe3103a4
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[clocks] IdealizedPll -> DividerOnlyClockGenerator
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2020-09-29 17:33:49 -07:00 |
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David Biancolin
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5b414f5829
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[clocks] Emit frequency summary for divider-only PLL model
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2020-09-29 16:59:37 -07:00 |
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David Biancolin
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a6ce850391
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[clocks] ClockDividerN: make first output edge occur on first input edge
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2020-09-29 16:19:05 -07:00 |
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Zitao Fang
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2aac38b4c8
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Fix CI bug
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2020-09-27 23:15:10 -07:00 |
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Zitao Fang
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f7407709d2
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Attempt to fix CI (2)
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2020-09-25 21:31:12 -07:00 |
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Zitao Fang
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751c0c300e
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Remove comments
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2020-09-25 20:49:18 -07:00 |
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Zitao Fang
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5243ee2a35
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Add HTIF args back to emulator.cc
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2020-09-25 20:36:07 -07:00 |
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Zitao Fang
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23847a6dca
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Merge branch 'dev' of github.com:ucb-bar/chipyard into verilator-makefile-fix
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2020-09-25 20:33:05 -07:00 |
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Zitao Fang
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942766ad86
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Merge branch 'dev' of github.com:ucb-bar/chipyard into sodor-integrate
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2020-09-25 11:41:40 -07:00 |
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David Biancolin
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b76972d34b
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Merge remote-tracking branch 'origin/dev' into diplomatic-clocks-pll-redux
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2020-09-25 11:02:51 -07:00 |
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David Biancolin
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67145c6ccd
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[clocking] Fix FireSim clock look up
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2020-09-25 10:05:28 -07:00 |
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David Biancolin
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1b3514f95f
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[clocks] Specify a default frequency for TraceGen
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2020-09-25 10:03:46 -07:00 |
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David Biancolin
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7b8a954d04
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[firechip] Rework FireSim clocking to be more similar to default CY targets
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2020-09-24 23:32:07 -07:00 |
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David Biancolin
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cc949aadab
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[clocking] Address some of Colin's PR comments
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2020-09-24 23:28:47 -07:00 |
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David Biancolin
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f6989a1968
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[clocks] Use the periphery frequency as the default
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2020-09-24 23:24:08 -07:00 |
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David Biancolin
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96bf702c3b
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[clocks] Factor out the PLL calculations into their own class
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2020-09-24 23:23:11 -07:00 |
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Zitao Fang
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6641c1f983
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Attempt to fix CI
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2020-09-24 22:42:49 -07:00 |
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David Biancolin
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84195d28bb
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[clocks] Don't override existing take frequency if present.
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2020-09-23 15:29:52 -07:00 |
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Jerry ZhaoandGitHub
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023d8096a9
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Merge pull request #677 from ucb-bar/smartelf2hex-fix
Fix smartelf2hex.sh creating files 64x the minimum size
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2020-09-22 17:04:45 -07:00 |
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Jerry Zhao
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d5660c01f3
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Bump esp-isa-sim for loadmem-fix add TLS segments to smartelf2hex
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2020-09-22 12:58:34 -07:00 |
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Jerry ZhaoandGitHub
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6c297e3179
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Fix smartelf2hex.sh creating files 64x the minimum size
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2020-09-22 11:08:52 -07:00 |
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Zitao Fang
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ae5fb8470b
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Remove unnecessary CI tests
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2020-09-19 10:27:20 -07:00 |
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Zitao Fang
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a02700a1d4
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Add documentation for sodor
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2020-09-18 23:14:47 -07:00 |
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Zitao Fang
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56d1d5b500
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Fix CI errors
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2020-09-18 22:42:19 -07:00 |
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Zitao Fang
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0c8771c35e
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Merge branch 'dev' of github.com:ucb-bar/chipyard into sodor-integrate
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2020-09-18 22:33:42 -07:00 |
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Zitao Fang
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a43400acb9
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Update CI
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2020-09-18 15:36:33 -07:00 |
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Jerry ZhaoandGitHub
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ba05b32f9c
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Merge pull request #673 from ucb-bar/serial-tl
Serial-tilelink backing memory
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2020-09-18 15:30:04 -07:00 |
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David Biancolin
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f36183d236
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[clocks] Update AssignerKey name and comment
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2020-09-18 11:28:31 -07:00 |
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Jerry Zhao
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bbf941c865
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Bump Firesim
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2020-09-18 10:43:58 -07:00 |
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Jerry Zhao
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aa355c7c1a
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Bump firesim
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2020-09-18 10:41:59 -07:00 |
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Jerry Zhao
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b9622c5132
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Merge remote-tracking branch 'origin/dev' into serial-tl
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2020-09-18 01:00:13 -07:00 |
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James Dunn
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9135cda959
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Bypassing AON for system.reset. Using reset_core in ArtyShell test harness, which is derived from Xilinx reset IP block's mb_reset. Changing dutReset to same reset_core.
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2020-09-17 13:43:28 -07:00 |
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David Biancolin
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ad147ec7f2
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[clocks] Remove dealiaser and node injector until they are needed
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2020-09-17 11:43:39 -07:00 |
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David Biancolin
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0f33ea3999
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[clocks] Stringly specified clock frequencies; DRY out schemes
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2020-09-17 11:41:05 -07:00 |
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David Biancolin
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6a26a350ee
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[clocks] Update dealiaser based on feedback
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2020-09-17 11:33:26 -07:00 |
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David Biancolin
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cfa7e30d95
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[clocks] Fix comment in ClockDividerN
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2020-09-17 11:32:51 -07:00 |
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Jerry ZhaoandGitHub
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43f746edb6
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Merge pull request #675 from ucb-bar/faster-ci
Improve CI build times by grouping similar builds
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2020-09-16 22:55:27 -07:00 |
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David Biancolin
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b8d3e4a66d
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Update Idealized PLL config
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2020-09-16 16:30:25 -07:00 |
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David Biancolin
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8e4dedcecf
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Remove require guard on divided configs
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2020-09-16 16:30:00 -07:00 |
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David Biancolin
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895bacea98
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WIP - Simple divider-only PLL generation flow
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2020-09-16 16:00:26 -07:00 |
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Jerry Zhao
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6874308981
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Address review comments
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2020-09-16 15:43:25 -07:00 |
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Jerry Zhao
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269af01a70
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Bump testchipip
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2020-09-16 13:51:33 -07:00 |
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Jerry Zhao
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36ccb12560
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Bump testchipip
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2020-09-16 10:29:03 -07:00 |
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Jerry Zhao
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aa8b7c15ec
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Reduce CI redundancy by grouping builds
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2020-09-16 00:57:05 -07:00 |
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abejgonzalez
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f1b40d51af
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Connected clocks | Exposed Master TL port
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2020-09-15 12:58:58 -07:00 |
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Zitao Fang
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1543acfacd
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Merge branch 'dev' of github.com:ucb-bar/chipyard into sodor-integrate
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2020-09-14 23:55:05 -07:00 |
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Zitao Fang
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642441e0a2
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Replaced memory and fixed 3-stage single port arbiter
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2020-09-14 23:54:52 -07:00 |
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Jerry Zhao
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0d8e87126c
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Deprecate support for on-chip SerialAdapter
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2020-09-14 19:43:32 -07:00 |
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Jerry Zhao
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f9cc1dc2c2
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Merge remote-tracking branch 'origin/dev' into serial-tl
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2020-09-14 19:35:43 -07:00 |
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Jerry ZhaoandGitHub
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23a199eccf
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Merge pull request #674 from ucb-bar/iocells-fix
Undo regression in iocells flexibility
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2020-09-14 19:32:37 -07:00 |
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