Jerry Zhao
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e93bc3bed7
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Fix Arty FPGA reset harness binder
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2023-04-01 13:53:56 -07:00 |
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Jerry Zhao
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6abf970ccb
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Fix ArtyJTAG matching
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2023-04-01 10:23:22 -07:00 |
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Jerry Zhao
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df2e5ad9dc
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Bump to latest rocket-chip/chisel3.5.6
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2023-03-28 16:48:27 -07:00 |
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Jerry Zhao
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2a4c5e6f88
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Bump testchipip
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2023-02-28 16:16:04 -08:00 |
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Jerry Zhao
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a50e7d3117
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Add more arty100t configs with configurable TSI-UART baudrate
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2023-02-15 21:45:09 -08:00 |
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Jerry Zhao
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fe51a1c7ce
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Remove arty100t IOBinders file
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2023-02-15 14:24:22 -08:00 |
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Jerry Zhao
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ec6bb45674
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Block Arty100T DDR during reset
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2023-02-15 11:15:48 -08:00 |
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Jerry Zhao
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61cc18749a
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Fix more bugs with arty100t
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2023-02-14 17:15:44 -08:00 |
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Jerry Zhao
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85fa9d1120
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Add ARTY100t bringup + TSI-over-UART
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2023-02-14 15:01:52 -08:00 |
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abejgonzalez
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292cc753ce
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Run pre-commit on all files
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2022-12-21 15:59:46 -08:00 |
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Abraham Gonzalez
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8e851b0285
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Merge pull request #1278 from Lorilandly/vc707fpga
Add support for VC707 FPGA board changelog:added
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2022-12-14 19:16:49 -08:00 |
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Haoan Li
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dab5720445
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expose functional pins and ports
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2022-12-13 16:53:31 +09:00 |
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-T.K.-
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1b7457d2fc
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FIX: fix Arty FPGA reset signal (#1257)
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2022-12-07 19:34:35 -08:00 |
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Lori Li
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0724431873
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Clean up code
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2022-11-30 16:56:09 +09:00 |
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Lori Li
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a2d1f16488
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revert module imp && fix for 4gb ram
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2022-11-30 03:51:56 +09:00 |
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Haoan Li
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fb793d7ee9
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Add support for VC707 fpga board
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2022-11-24 16:08:15 +09:00 |
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James Dunn
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8e59db02fd
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Merge pull request #968 from duyhieubui/master
Fixes UART portmap for Arty.
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2021-10-13 13:25:10 -07:00 |
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Jerry Zhao
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f668ffdb03
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Switch PRCI to HarnessBinder/IOBinders
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2021-09-29 11:39:52 -07:00 |
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Duy-Hieu Bui
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d9858c1dc8
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Fixes UART portmap for Arty.
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2021-09-03 05:02:36 +07:00 |
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Abraham Gonzalez
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985faa4c8e
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Small comment updates + cleanup
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2021-04-03 12:55:27 -07:00 |
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Abraham Gonzalez
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be13781a1c
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Set both MBUS/PBUS in configs | Add simple check for correct clocks
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2021-04-02 16:43:59 -07:00 |
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Abraham Gonzalez
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5a41c5d9ac
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Use multi-clock config. frags to determine VCU118 clk freq
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2021-04-01 16:21:44 -07:00 |
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Abraham Gonzalez
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f334d5799f
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Support 30MiB payloads - VCU118 FPGA
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2021-04-01 16:21:16 -07:00 |
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Jerry Zhao
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ed2bfa8249
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Don't pass JTAG oe signal off-chip (#832)
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2021-03-24 01:08:46 -07:00 |
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abejgonzalez
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09ef82cabf
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Update harnessClk/Rst naming to buildtop | Small docs cleanup
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2021-03-22 13:11:12 -07:00 |
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abejgonzalez
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9957538d38
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Enable support for pullup R's on GPIOs
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2021-02-25 13:54:53 -08:00 |
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abejgonzalez
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4d3ff26a73
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Bump testchipip
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2021-01-04 15:36:00 -08:00 |
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abejgonzalez
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b797077334
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Fix Arty documentation link
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2020-12-27 22:00:06 -08:00 |
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abejgonzalez
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f1fdab5bd3
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Move TL mem switch frag to CY | Add require to not have TL/AXI backing mem
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2020-11-23 16:58:34 -08:00 |
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abejgonzalez
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8f6de22e72
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Fixed TinyRocketConfig | Small cleanup to VCU118/Arty configs
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2020-11-23 16:30:39 -08:00 |
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abejgonzalez
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661a7701a7
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Share DigitalTop/ChipyardSystem | Fix small naming compile error
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2020-11-23 15:46:03 -08:00 |
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James Dunn
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95e8365105
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Small change to Arty reset binder name, per Jerry's PR comment.
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2020-11-18 16:53:37 -08:00 |
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abejgonzalez
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d94a8efd43
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Fix TLMemPort comment | Use Option instead of NoSimulator
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2020-11-15 15:44:38 -08:00 |
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abejgonzalez
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c8add488ad
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Reduce BOOM default freq. (play it safe)
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2020-11-15 14:31:14 -08:00 |
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abejgonzalez
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55f19f79d3
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Address fpga srcs
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2020-11-12 15:39:29 -08:00 |
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abejgonzalez
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7ca3be236c
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Bump bringup VCU118 | Ignore HTIF if no-debug module
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2020-11-12 11:47:16 -08:00 |
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abejgonzalez
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082b230452
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Add missing file
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2020-11-08 17:51:21 -08:00 |
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abejgonzalez
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244205e2b4
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Separate new sys_clk and ddr2 from TSI
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2020-11-08 17:49:32 -08:00 |
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Abraham Gonzalez
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5a4cad0172
|
Merge pull request #6 from ucb-bar/local-fpga-support-docs
Local fpga support docs
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2020-11-06 21:03:15 -08:00 |
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abejgonzalez
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c5e8fecb5c
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Small renaming and cleanup
|
2020-11-06 21:00:18 -08:00 |
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Abraham Gonzalez
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9144e3c706
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Fix pin mappings for TSI DDR
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2020-11-06 20:51:11 -08:00 |
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James Dunn
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98fcea7b57
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Adding initial Arty documentation; will be expanded further.
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2020-11-06 17:25:05 -08:00 |
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abejgonzalez
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7baa1341ee
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Use 2nd system clock for TSI DDR | Small cleanups
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2020-11-06 16:34:45 -08:00 |
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abejgonzalez
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6aae66c54f
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Add TSI Host Widget
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2020-11-06 15:50:28 -08:00 |
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Abraham Gonzalez
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b0eed5075f
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[temp] start integrating tsi host widget
|
2020-11-06 10:57:55 -08:00 |
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abejgonzalez
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c721d897f3
|
Point to SiFive license | Add require on Arty
|
2020-11-06 10:18:10 -08:00 |
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abejgonzalez
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84508bee6e
|
More FPGA prototyping docs
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2020-11-05 21:51:25 -08:00 |
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abejgonzalez
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313fa4f129
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Merge branch 'local-fpga-support' into local-fpga-support-docs
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2020-11-05 21:24:03 -08:00 |
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abejgonzalez
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b0fc0457aa
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Use Chipyard configs as base (Arty)
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2020-11-05 20:46:03 -08:00 |
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abejgonzalez
|
9a5b67bf8c
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Use Chipyard configs as a base (VCU118)
|
2020-11-05 20:30:49 -08:00 |
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