40 lines
1.1 KiB
Scala
40 lines
1.1 KiB
Scala
package chipyard.fpga.arty
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import chisel3._
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import freechips.rocketchip.diplomacy.{LazyModule}
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import org.chipsalliance.cde.config.{Parameters}
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import sifive.fpgashells.shell.xilinx.artyshell.{ArtyShell}
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import chipyard.harness.{ApplyHarnessBinders, BuildTop, HasHarnessSignalReferences}
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import chipyard.iobinders.{HasIOBinders}
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class ArtyFPGATestHarness(override implicit val p: Parameters) extends ArtyShell with HasHarnessSignalReferences {
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val lazyDut = LazyModule(p(BuildTop)(p)).suggestName("chiptop")
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// Convert harness resets from Bool to Reset type.
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val hReset = Wire(Reset())
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hReset := ~ck_rst
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val dReset = Wire(AsyncReset())
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dReset := reset_core.asAsyncReset
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// default to 32MHz clock
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withClockAndReset(clock_32MHz, hReset) {
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val dut = Module(lazyDut.module)
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}
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val buildtopClock = clock_32MHz
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val buildtopReset = hReset
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val success = false.B
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val dutReset = dReset
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// must be after HasHarnessSignalReferences assignments
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lazyDut match { case d: HasIOBinders =>
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ApplyHarnessBinders(this, d.lazySystem, d.portMap)
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}
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}
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