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Author SHA1 Message Date
Jerry Zhao fba75e7a74 Bump constellation with improved TL-noc 2023-10-19 23:40:33 -07:00
Jerry ZhaoandGitHub f80426ef9d Merge pull request #1631 from ucb-bar/jerryz123-patch-5 
[vlsi][ci skip] Fix tutorial.mk so that INPUT_CONFS override only affects tutorials
 2023-10-19 11:35:51 -07:00
Jerry ZhaoandGitHub 77ee5906e2 [vlsi][ci skip] Fix INPUT_CONFS override in tutorial.mk 2023-10-19 11:19:56 -07:00
Jerry Zhao 1d9dba517b Fix unassigned clocks due to removing implicit clock from BaseSubsystem 2023-10-18 18:59:22 -07:00
Jerry Zhao 646ba4fba7 Bump testchipip 2023-10-18 00:38:52 -07:00
Jerry Zhao 686d9a5f44 Bump rocket-chip 2023-10-18 00:27:05 -07:00
Jerry Zhao e8aa68c65c Tiles do not generate interrupts 2023-10-17 17:05:45 -07:00
Jerry Zhao 5f51da3db3 Fix HasChipyardPRCI typos 2023-10-17 15:56:22 -07:00
Jerry Zhao 7cc03f40eb Add test for clustered-rocket config 2023-10-17 14:39:39 -07:00
Jerry Zhao aa057239f2 Bump rocket-chip + submodules for new clustered-tile API 2023-10-17 14:38:28 -07:00
Abraham GonzalezandGitHub adc0f0ed0f Merge pull request #1625 from ucb-bar/bump-barstools 
Bump barstools
 2023-10-16 21:42:19 -07:00
Abraham GonzalezandGitHub 9ba58f89f1 Merge branch 'main' into bump-barstools 2023-10-16 16:22:12 -07:00
abejgonzalez b1f3119676 Bump barstools 2023-10-16 16:18:42 -07:00
Jerry ZhaoandGitHub 2b16b9bad1 Merge pull request #1610 from ucb-bar/port_api 
Add PortAPI between IO and Harness blocks
 2023-10-15 12:56:11 -07:00
Jerry ZhaoandGitHub 6bd2e9dddb [ci skip] Re-add suggestName for axi4 mmio mem 2023-10-13 17:36:41 -07:00
Jerry Zhao deab3b11b6 Fix UARTAdapter div bits 2023-10-12 15:37:03 -07:00
Jerry Zhao 3cbcf6b6e8 Fix TSIBridge loadmem param 2023-10-11 15:01:39 -07:00
Jerry Zhao 894ee63061 Make chipParameters not private 2023-10-11 14:59:49 -07:00
Jerry ZhaoandGitHub 73efea08bf Merge pull request #1620 from ucb-bar/marshal-rng-init-bump 
Bump FireMarshal for linux rng init fix
 2023-10-11 14:11:40 -07:00
raghav-g13 26d4e45b27 bumping marshal for linux rng init fix 2023-10-11 01:43:36 +00:00
Jerry Zhao 0ebab140ff Update nexysvideo to Port api 2023-10-09 11:49:38 -07:00
Jerry Zhao 8ecd7bfa89 Merge remote-tracking branch 'origin/main' into port_api 2023-10-09 11:18:00 -07:00
Jerry ZhaoandGitHub d9cec6ad34 Merge pull request #1616 from milovanovic/main 
Adds support for Digilent Nexys Video FPGA board.
 2023-10-09 11:05:57 -07:00
Jerry ZhaoandGitHub 0665f986ea Merge pull request #1614 from JL102/script-trycatch 
Added useful "Build script exited at step X" errors for each step in build-setup.sh
 2023-10-09 09:30:11 -07:00
Jordan LeesandGitHub 5bbebb83dc Merge branch 'main' into script-trycatch 2023-10-07 22:13:24 -07:00
Jerry Zhao 8d11dde7cb Fix UARTPort freqMHz 2023-10-07 00:27:15 -07:00
Jerry Zhao 5145f4f243 Bump firesim 2023-10-06 17:55:49 -07:00
Jerry Zhao b949324d5a Fix FireSim UARTBridge 2023-10-06 17:55:14 -07:00
Jerry Zhao a4cb114657 Fix UARTAdapter divisor 2023-10-06 17:00:06 -07:00
JL102 9b557227a3 Remove now-unused build-step scripts 2023-10-06 19:01:47 -04:00
JL102 a7993db08e I think now I put &&s everywhere that is necessary 2023-10-06 19:00:11 -04:00
JL102 aded25fee0 Made indentation consistent 2023-10-06 18:49:10 -04:00
JL102 b76ab6b5b0 Replaced "try-catch" with a more special-purpose set of functions 
This also fixed the weird issue I was experiencing where the try-catch in step 1 caused step 3 to break
 2023-10-06 18:43:52 -04:00
joonho hwangboandGitHub a524adb1b9 Fix icenet-loopback clock and reset domain (#1612) 
* Fix

* Bump icenet

* revert icenet bump | fix harnessbinders
 2023-10-06 08:34:15 -07:00
Jerry Zhao e6203bb25c Fix fsim supernode memmodel 2023-10-05 23:56:29 -07:00
Jerry Zhao 8fb4ba5675 Fix UARTPort freqMHz 2023-10-05 21:03:34 -07:00
Jerry Zhao eb3a0aecf4 Add PortAPI between IO and Harness blocks 2023-10-05 15:02:56 -07:00
Vladimir Milovanovićandpznikola 3d96cf5bc9 Adds initial Nexys Video board support. 
Co-authored-by: pznikola <p.z.nikola@etf.rs>
 2023-10-05 23:01:29 +02:00
Vladimir Milovanović 7debb5f52d Bump fpga-shells. 2023-10-06 09:54:42 +02:00
Vladimir Milovanović 3c9818024b Bump rocket-dsp-utils. 2023-10-06 09:54:42 +02:00
Vladimir Milovanović 9a9e201507 Bump fixedpoint. 2023-10-06 09:54:42 +02:00
Vladimir Milovanović 6eacd0aa75 Bump dsptools. 2023-10-06 09:54:42 +02:00
Jerry ZhaoandGitHub 6b5d55ccd4 Merge pull request #1615 from hansungk/fix-insert-includes-python 
Make scripts/insert-includes.py use Python from conda env
 2023-10-05 11:36:06 -07:00
Hansung Kim 921b0c062e Use env python interpreter in insert-includes.py 
This fixes failing CI for CVA6/nvdla on a system that does not have a
/usr/bin/python interpreter by making the script use one from conda env.
 2023-10-05 11:15:42 -07:00
Jordan LeesandGitHub 3b7057cbfc Merge branch 'ucb-bar:main' into script-trycatch 2023-10-04 23:34:19 -07:00
JL102 6b70dd6d39 Added "try-catch" to all build-setup steps 
This was the only way I knew how to display the step at which the build-setup process failed.
I've personally experienced failures at multiple of the build steps, and before I got used to Chipyard,
it was hard to figure out which step was the culprit. With this, users should have a bit more info to
troubleshoot their issues. For some of the build steps that required multiple lines, I figured it made
more sense to put them into a sub-script, rather than putting a && at the end of each line. But for the
firesim one for example, since it was two .sh calls, I just put a && after the first one, inside of the
try block, to make sure both lines run.
 2023-10-05 02:17:25 -04:00
-T.K.- 8fa8be5669 ADD: bump testchipip 2023-09-27 10:54:57 -07:00
Jerry ZhaoandGitHub adebd634b4 Fix Arty100T Verilog build (#1608) 
* Bump rocket-chip
* Bump fpga-shells
* Add Arty100T Verilog build to CI
* Fix Arty100T harness disconnected LEDs
 2023-09-27 13:03:37 +02:00
-T.K.- f3c7ecf8ba REFACTOR: change bootaddr and reset vector address 2023-09-23 19:17:54 -07:00
Jerry ZhaoandGitHub 8c1319073c Merge pull request #1601 from ucb-bar/no-mcaxiram 
Remove MultiClockHarnessAXIMem
 2023-09-20 21:26:40 -07:00