Commit Graph

18 Commits

Author SHA1 Message Date
David Biancolin
b303cf6e81 Rocket Chip Stage/Phase Bump (#503)
[WIP] Minimally elaborating design

Bring up a feature-complete Chipyard stage

Pull in Makefrag generation; Bump submodules

Update config generation, and global reset scheme

Bump submodules; clean up

Bump FireSim

Remove some unhygenic comments / WS

Remove the rocketchip subproject

[CI] Lengthen ariane tests timeout

Address some remaining reviewer comments

[firechip] Refresh a Field that cannot be used across repeated instantiations

Bump all submodules
2020-04-18 17:54:27 +00:00
David Biancolin
d49c30560c Merge remote-tracking branch 'origin/dev' into diplomatic-bridges 2020-04-06 23:59:19 -07:00
David Biancolin
ba19987984 [firechip] Label FASED instances with an associated memory region name 2020-04-04 18:38:34 -07:00
John Wright
1f98c84210 Add ChipTop to enable real chip configs with IO cells, etc. (#480)
This adds an additional layer (ChipTop) between the System module and the TestHarness. The IOBinder API is now changed to take only a single parameter (an Any) and return a 3 things: The IO port(s), the IO cell(s), and a function to call inside the test harness, which is analogous to the old IOBinder function, except that it takes a TestHarness object as an argument instead of (clock, reset, success).
* A new Top-level module, ChipTop, has been created. ChipTop instantiates a "system" module specified by BuildSystem.
* BuildTop now builds a ChipTop dut module in the TestHarness by default
* A new BuildSystem key has been added, which by default builds DigitalTop (previously just called Top)
* The IOBinders API has changed. IOBinders are now called inside of ChipTop and return a tuple3 of (IO ports, IO cells, harness functions). The harness functions are now called inside the TestHarness (this is analogous to the previous IOBinder functions).
* IO cell models have been included in ChipTop. These can be replaced with real IO cells for tapeout, or used as-is for simulation.
* The default for the TOP make variable is now ChipTop (was Top)
2020-04-01 14:03:56 -07:00
David Biancolin
d80c2f7c08 Merge remote-tracking branch 'origin/dev' into firesim-multiclock
[ci skip]
2020-03-18 09:22:17 -07:00
Abraham Gonzalez
d0bec3fba7 Ariane Integration (#448)
* [ariane/make] integrate ariane | have verilator be installed on path not in makefile

* [misc] warn on verilator not found | search for v files | cleanup build.sbt + .gitignore

* [firesim] bump

* [ci] add midas ariane tests

* [docker/ci] use new docker-image with verilator | re-elab on v changes for ariane | address comments

* [ci] remove references to local verilator install

* [verilator] update flags

* [verilator] minimal set of flags for ariane

* [ariane] bump ariane to master

* [ci] revert to 4.016 verilator

* [ci] install verilator to ci server | misc compile fixes

* [ci/make] add longer ci timeout | update when assert is added in verilator sim

* [firesim] bump for misc. updates

* [make/ci] cleanup makefile and remove firesim tests of it

* [docs/firesim] bump and clean docs

* [firesim] bump

* [ci] use remote verilator for midas tests

* [misc] cleanup built.sbt more

* [firesim] bump

* [misc] bump build.sbt patch for tutorials

* [firesim/ci] cleanup and bump firesim
2020-03-09 18:06:41 -07:00
Jerry Zhao
708a5fb9a6 Address generator unification PR reviews 2020-02-23 22:53:14 -08:00
Jerry Zhao
701ea7c355 Add new type of IOBinder macro 2020-02-13 12:33:28 -08:00
Jerry Zhao
0f56c4ce44 Unify configs between Chipyard and FireSim 2020-02-13 12:33:28 -08:00
Jerry Zhao
ebfa545344 Generator unification 2020-02-13 12:33:28 -08:00
David Biancolin
d19ca81e61 Merge remote-tracking branch 'origin/dev' into firesim-multiclock 2020-02-13 12:14:04 -08:00
Jerry Zhao
ac5235e5ed Revamp the config system for Top/Harness (#347)
* Refactor how Configs parameterize the Top and TestHarnesses

* Bump sha3, testchipip, icenet, firesim
2020-01-21 20:44:54 -08:00
David Biancolin
3fbc074b01 [firechip] Instantiate multiple TracerV bridges 2020-01-17 17:56:37 -08:00
Colin Schmidt
86a473dbf6 Bump all submodules for chisel 3.2.0 and rocket-chip august-2019 (#358)
* Bump all submodules for chisel 3.2.0 and rocket-chip august-2019

* Fix subprojects that aren't tested from normal sims

* Fix firechip for chisel 3.2.0 and rc bump

* Bump boom for bug fix rebase

* [sbt] Don't rely on target-rtl symlink when FireSim is top [no ci]

* Bump boom for rc bump fix to bug fix

* Bump FireSim for CI check

* Bump FireSim

* Bump submodules after merge
2019-12-12 13:39:09 -08:00
David Biancolin
12485b8e5c [firesim] Update TraceGen BridgeBinder 2019-11-20 13:31:11 -08:00
David Biancolin
e3b30dbd83 [FireChip] Use clock in BridgeBinders 2019-11-01 17:17:57 -07:00
Howard Mao
05af2f9a9c Fix tracegen target and add to CI 2019-10-21 09:55:40 -07:00
David Biancolin
aa6e09f800 Rename Endpoint -> Bridge 2019-10-06 03:32:50 +00:00