83 lines
2.9 KiB
Scala
83 lines
2.9 KiB
Scala
//See LICENSE for license details.
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package firesim.firesim
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import chisel3._
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import freechips.rocketchip.config.{Field, Config}
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import freechips.rocketchip.diplomacy.{LazyModule}
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import freechips.rocketchip.devices.debug.HasPeripheryDebugModuleImp
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import freechips.rocketchip.subsystem.{CanHaveMasterAXI4MemPortModuleImp}
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import sifive.blocks.devices.uart.HasPeripheryUARTModuleImp
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import testchipip.{HasPeripherySerialModuleImp, HasPeripheryBlockDeviceModuleImp}
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import icenet.HasPeripheryIceNICModuleImpValidOnly
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import junctions.{NastiKey, NastiParameters}
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import midas.models.{FASEDBridge, AXI4EdgeSummary, CompleteConfig}
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import firesim.bridges._
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import firesim.configs.MemModelKey
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import firesim.util.RegisterBridgeBinder
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import tracegen.HasTraceGenTilesModuleImp
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class WithTiedOffDebug extends RegisterBridgeBinder({ case target: HasPeripheryDebugModuleImp =>
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target.debug.clockeddmi.foreach({ cdmi =>
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cdmi.dmi.req.valid := false.B
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cdmi.dmi.req.bits := DontCare
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cdmi.dmi.resp.ready := false.B
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cdmi.dmiClock := false.B.asClock
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cdmi.dmiReset := false.B
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})
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Seq()
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})
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class WithSerialBridge extends RegisterBridgeBinder({
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case target: HasPeripherySerialModuleImp => Seq(SerialBridge(target.clock, target.serial)(target.p))
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})
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class WithNICBridge extends RegisterBridgeBinder({
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case target: HasPeripheryIceNICModuleImpValidOnly => Seq(NICBridge(target.clock, target.net)(target.p))
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})
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class WithUARTBridge extends RegisterBridgeBinder({
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case target: HasPeripheryUARTModuleImp => target.uart.map(u => UARTBridge(target.clock, u)(target.p))
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})
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class WithBlockDeviceBridge extends RegisterBridgeBinder({
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case target: HasPeripheryBlockDeviceModuleImp => Seq(BlockDevBridge(target.clock ,target.bdev, target.reset.toBool)(target.p))
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})
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class WithFASEDBridge extends RegisterBridgeBinder({
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case t: CanHaveMasterAXI4MemPortModuleImp =>
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implicit val p = t.p
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(t.mem_axi4 zip t.outer.memAXI4Node).flatMap({ case (io, node) =>
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(io zip node.in).map({ case (axi4Bundle, (_, edge)) =>
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val nastiKey = NastiParameters(axi4Bundle.r.bits.data.getWidth,
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axi4Bundle.ar.bits.addr.getWidth,
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axi4Bundle.ar.bits.id.getWidth)
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FASEDBridge(t.clock, axi4Bundle, t.reset.toBool,
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CompleteConfig(p(firesim.configs.MemModelKey), nastiKey, Some(AXI4EdgeSummary(edge))))
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})
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}).toSeq
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})
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class WithTracerVBridge extends RegisterBridgeBinder({
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case target: HasTraceIOImp => TracerVBridge(target.traceIO)(target.p)
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})
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class WithTraceGenBridge extends RegisterBridgeBinder({
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case target: HasTraceGenTilesModuleImp =>
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Seq(GroundTestBridge(target.clock, target.success)(target.p))
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})
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// Shorthand to register all of the provided bridges above
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class WithDefaultFireSimBridges extends Config(
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new WithTiedOffDebug ++
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new WithSerialBridge ++
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new WithNICBridge ++
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new WithUARTBridge ++
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new WithBlockDeviceBridge ++
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new WithFASEDBridge ++
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new WithTracerVBridge
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)
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