Commit Graph

15 Commits

Author SHA1 Message Date
Jerry Zhao
e93bc3bed7 Fix Arty FPGA reset harness binder 2023-04-01 13:53:56 -07:00
Jerry Zhao
6abf970ccb Fix ArtyJTAG matching 2023-04-01 10:23:22 -07:00
Jerry Zhao
df2e5ad9dc Bump to latest rocket-chip/chisel3.5.6 2023-03-28 16:48:27 -07:00
Lori Li
0724431873 Clean up code 2022-11-30 16:56:09 +09:00
Duy-Hieu Bui
d9858c1dc8 Fixes UART portmap for Arty. 2021-09-03 05:02:36 +07:00
Jerry Zhao
ed2bfa8249 Don't pass JTAG oe signal off-chip (#832) 2021-03-24 01:08:46 -07:00
abejgonzalez
09ef82cabf Update harnessClk/Rst naming to buildtop | Small docs cleanup 2021-03-22 13:11:12 -07:00
abejgonzalez
c721d897f3 Point to SiFive license | Add require on Arty 2020-11-06 10:18:10 -08:00
abejgonzalez
b0fc0457aa Use Chipyard configs as base (Arty) 2020-11-05 20:46:03 -08:00
abejgonzalez
a281869041 Fix Arty merge and errors from CY bump 2020-11-05 15:04:44 -08:00
abejgonzalez
a7ab0dab59 Updated VCU118 | Bumped naming on Arty 2020-11-05 13:59:10 -08:00
James Dunn
895dcd6831 referencing fully qualified chipyard.harness.OverrideHarnessBinder to debug import issue. 2020-10-11 11:12:33 -07:00
James Dunn
dca56cd858 Removing redefinitions of HasHarnessSignalReferences and HasTestHarnessFunctions in TestHarness.scala. 2020-10-10 19:55:02 -07:00
James Dunn
54acfe71fc Some HarnessBinder testing with Jerry's debug suggestions. 2020-10-10 13:45:27 -07:00
dunn
7d1a1539e6 Initial pass at HarnessBinders for Arty. 2020-10-09 23:17:36 -07:00