73 lines
2.4 KiB
Scala
73 lines
2.4 KiB
Scala
package chipyard.fpga.arty
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import chisel3._
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import chisel3.experimental.{Analog}
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import freechips.rocketchip.config.{Field, Config, Parameters}
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import freechips.rocketchip.diplomacy.{LazyModule, LazyModuleImpLike}
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import freechips.rocketchip.amba.axi4.{AXI4Bundle, AXI4SlaveNode, AXI4MasterNode, AXI4EdgeParameters}
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import freechips.rocketchip.devices.debug._
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import freechips.rocketchip.jtag.{JTAGIO}
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import freechips.rocketchip.system.{SimAXIMem}
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import freechips.rocketchip.subsystem._
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import sifive.blocks.devices.gpio._
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import sifive.blocks.devices.uart._
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import sifive.blocks.devices.spi._
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import barstools.iocell.chisel._
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import testchipip._
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import chipyard.harness.OverrideHarnessBinder
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import chipyard.HasHarnessSignalReferences
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import chipyard.iobinders.GetSystemParameters
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import tracegen.{TraceGenSystemModuleImp}
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import icenet.{CanHavePeripheryIceNIC, SimNetwork, NicLoopback, NICKey, NICIOvonly}
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import scala.reflect.{ClassTag}
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import sifive.fpgashells.ip.xilinx.{IBUFG, IOBUF, PULLUP, PowerOnResetFPGAOnly}
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class WithArtyJTAGHarnessBinder extends OverrideHarnessBinder({
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(system: HasPeripheryDebugModuleImp, th: ArtyFPGATestHarness, ports: Seq[JTAGIO]) => {
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// (system: HasPeripheryDebugModuleImp, th: ArtyFPGATestHarness, ports: Seq[Data]) => {
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// ports.map {
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// case d: ClockedDMIIO =>
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// // Want to error here.
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// case j: JTAGIO =>
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// //val dtm_success = WireInit(false.B)
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// //when (dtm_success) { th.success := true.B }
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// //val jtag = Module(new SimJTAG(tickDelay=3)).connect(j, th.harnessClock, th.harnessReset.asBool, ~(th.harnessReset.asBool), dtm_success)
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// j.TCK.i.ival := IBUFG(IOBUF(th.jd_2).asClock).asUInt
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// IOBUF(th.jd_5, j.TMS)
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// PULLUP(th.jd_5)
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// IOBUF(th.jd_4, j.TDI)
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// PULLUP(th.jd_4)
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// IOBUF(th.jd_0, j.TDO)
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// // mimic putting a pullup on this line (part of reset vote)
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// th.SRST_n := IOBUF(th.jd_6)
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// PULLUP(th.jd_6)
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// IOBUF(th.jd_1, j.TRSTn)
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// PULLUP(th.jd_1)
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// }
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Nil
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}
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})
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class WithArtyUARTHarnessBinder extends OverrideHarnessBinder({
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(system: HasPeripheryUARTModuleImp, th: ArtyFPGATestHarness, ports: Seq[UARTPortIO]) => {
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// (system: HasPeripheryUARTModuleImp, th: ArtyFPGATestHarness, ports: Seq[UARTPortIO]) => {
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// UARTAdapter.connect(ports)(system.p)
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// IOBUF(th.ck_io(2), ports.txd)
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// IOBUF(th.ck_io(3), ports.rxd)
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Nil
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}
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}) |