Jerry Zhao
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e7f10348b0
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Merge remote-tracking branch 'origin/main' into clusters
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2023-12-15 16:46:51 -08:00 |
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Jerry Zhao
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a5597fd32f
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Support using HarnessBinders without IOBinders
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2023-10-25 11:49:16 -07:00 |
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Jerry Zhao
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b4d4e54f9c
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Bump fpga-shells
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2023-10-24 18:24:44 -07:00 |
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Jerry Zhao
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078bce1323
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Bump to chisel3.6
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2023-07-05 10:32:55 -07:00 |
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jerryho
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9844deb172
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using dp(ExtTLMem).get.master.beatBytes to obtain MemoryBus data width
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2023-05-27 18:12:56 +08:00 |
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jerryho
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45eeee5092
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fix the data field width mismatch between AXI that goes to MIG core and that of the Memory Bus
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2023-05-26 16:08:59 +08:00 |
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Jerry Zhao
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57f5168408
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Set number of idbits correctly for fpga ddr
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2023-05-15 00:04:12 -07:00 |
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Jerry Zhao
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f4739be632
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Update multi-chip API for harnesses
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2023-05-15 00:03:22 -07:00 |
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Jerry Zhao
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2077e4304d
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Explicitly provide refClockFreqMHz to harnessClockInstantiator
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2023-05-13 11:18:03 -07:00 |
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Jerry Zhao
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b8e95e0305
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Rename implicit clock/reset to referenceclock/reset
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2023-05-12 15:11:44 -07:00 |
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Jerry Zhao
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607c2b5a73
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Unify multi-node btw chipyard/firechip | unify harness clocking
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2023-05-12 08:41:34 -07:00 |
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Jerry Zhao
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64ad77bbcf
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Make FPGA flows use the harnessClockInstantiator
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2023-05-11 15:04:04 -07:00 |
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Jerry Zhao
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ac281daa78
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Move TestHarness to chipyard.harness, make chipyard/harness directory
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2023-05-08 08:00:56 -07:00 |
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Jerry Zhao
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df2e5ad9dc
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Bump to latest rocket-chip/chisel3.5.6
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2023-03-28 16:48:27 -07:00 |
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Jerry Zhao
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85fa9d1120
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Add ARTY100t bringup + TSI-over-UART
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2023-02-14 15:01:52 -08:00 |
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Lori Li
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0724431873
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Clean up code
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2022-11-30 16:56:09 +09:00 |
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Jerry Zhao
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f668ffdb03
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Switch PRCI to HarnessBinder/IOBinders
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2021-09-29 11:39:52 -07:00 |
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Abraham Gonzalez
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be13781a1c
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Set both MBUS/PBUS in configs | Add simple check for correct clocks
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2021-04-02 16:43:59 -07:00 |
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Abraham Gonzalez
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5a41c5d9ac
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Use multi-clock config. frags to determine VCU118 clk freq
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2021-04-01 16:21:44 -07:00 |
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abejgonzalez
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09ef82cabf
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Update harnessClk/Rst naming to buildtop | Small docs cleanup
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2021-03-22 13:11:12 -07:00 |
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abejgonzalez
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661a7701a7
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Share DigitalTop/ChipyardSystem | Fix small naming compile error
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2020-11-23 15:46:03 -08:00 |
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abejgonzalez
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55f19f79d3
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Address fpga srcs
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2020-11-12 15:39:29 -08:00 |
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abejgonzalez
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244205e2b4
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Separate new sys_clk and ddr2 from TSI
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2020-11-08 17:49:32 -08:00 |
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Abraham Gonzalez
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5a4cad0172
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Merge pull request #6 from ucb-bar/local-fpga-support-docs
Local fpga support docs
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2020-11-06 21:03:15 -08:00 |
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abejgonzalez
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c5e8fecb5c
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Small renaming and cleanup
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2020-11-06 21:00:18 -08:00 |
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abejgonzalez
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7baa1341ee
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Use 2nd system clock for TSI DDR | Small cleanups
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2020-11-06 16:34:45 -08:00 |
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abejgonzalez
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84508bee6e
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More FPGA prototyping docs
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2020-11-05 21:51:25 -08:00 |
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abejgonzalez
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255e88fe8f
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Initial outline of FPGA prototyping docs
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2020-11-05 17:06:34 -08:00 |
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abejgonzalez
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a7ab0dab59
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Updated VCU118 | Bumped naming on Arty
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2020-11-05 13:59:10 -08:00 |
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Abraham Gonzalez
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0eca51ba4d
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Reorganize into bringup/simple | Bump sifive-blocks
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2020-10-27 12:57:34 -07:00 |
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abejgonzalez
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7f387a254b
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Working up until the MMC attachment
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2020-10-14 23:09:49 -07:00 |
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abejgonzalez
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dcac9b79df
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Basic working with UART
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2020-10-14 16:15:10 -07:00 |
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abejgonzalez
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dda7622c29
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temp commit
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2020-10-14 14:49:22 -07:00 |
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abejgonzalez
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8257775e96
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Connect DDR from harness
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2020-10-12 21:50:50 -07:00 |
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abejgonzalez
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f1b40d51af
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Connected clocks | Exposed Master TL port
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2020-09-15 12:58:58 -07:00 |
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abejgonzalez
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72c0f4b3d3
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Add GPIO Overlay
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2020-09-13 16:37:20 -07:00 |
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abejgonzalez
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69bf39bf13
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Added more overlays | Closer to bringup platform
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2020-09-12 18:18:13 -07:00 |
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abejgonzalez
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e98a0f172f
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Connected UART nicely
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2020-09-11 16:55:25 -07:00 |
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abejgonzalez
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56eead4053
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NOT WORKING: VCU118 Commit
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2020-09-08 17:04:56 -07:00 |
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