 abejgonzalezandjoey0320
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c472e22223
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Update FPGA makefile | Reorg firtool args
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2023-01-09 10:33:38 -08:00 |
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Haoan Li
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37f2578f6c
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Bump fpga-shells version
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2022-11-24 16:18:03 +09:00 |
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Haoan Li
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fb793d7ee9
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Add support for VC707 fpga board
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2022-11-24 16:08:15 +09:00 |
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Abraham GonzalezandGitHub
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af78c9cadf
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Remove extra spaces in FPGA makefile
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2022-03-02 15:45:27 +01:00 |
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Tingyuan LIANGandGitHub
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d06abdb419
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Swap two arguments to resolve bug
**Related issue**: N/A
**Type of change**: bug fix
**Impact**: other
**Release Notes**
The string of path for "-ip-vivado-tcls" could be empty ("")
For example, run "make SUB_PROJECT=arty bitstream" will get errors due the argument parsing in [prologue.tcl](https://github.com/sifive/fpga-shells/blob/d4b3878e4f5cf5c4621dbfe9b0bda1ed0dd3b995/xilinx/common/tcl/prologue.tcl)
Swaping the two arguments can resolve bug.
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2021-08-12 23:22:41 +08:00 |
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abejgonzalez
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16cdc88c52
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Small comment + org. fix | Remove extra mkdirs
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2021-05-12 16:42:05 -07:00 |
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abejgonzalez
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2874c98802
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Add sim_files.f to fpga
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2021-05-06 22:11:58 -07:00 |
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abejgonzalez
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1b4826ad82
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Generalize debug-bitstream
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2020-11-12 16:20:22 -08:00 |
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abejgonzalez
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d4d989ce0f
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Rename make target to bitstream | Delete unused make stuff / tcl
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2020-11-12 15:41:05 -08:00 |
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abejgonzalez
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a281869041
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Fix Arty merge and errors from CY bump
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2020-11-05 15:04:44 -08:00 |
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abejgonzalez
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356fa70c3c
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Update fpga-shells submodule | Fix Arty Makefile lines
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2020-11-05 11:16:17 -08:00 |
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Abraham Gonzalez
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0eca51ba4d
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Reorganize into bringup/simple | Bump sifive-blocks
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2020-10-27 12:57:34 -07:00 |
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Abraham Gonzalez
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db73cab164
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Add BootROM | Fix ResetWrangler for DDR | Add scripts
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2020-10-20 21:20:11 -07:00 |
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Abraham Gonzalez
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dd358f45ab
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UART Working... Bumped to newer fpga-shells
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2020-10-19 11:29:25 -07:00 |
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abejgonzalez
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7f387a254b
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Working up until the MMC attachment
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2020-10-14 23:09:49 -07:00 |
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abejgonzalez
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dcac9b79df
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Basic working with UART
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2020-10-14 16:15:10 -07:00 |
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abejgonzalez
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e98a0f172f
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Connected UART nicely
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2020-09-11 16:55:25 -07:00 |
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abejgonzalez
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56eead4053
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NOT WORKING: VCU118 Commit
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2020-09-08 17:04:56 -07:00 |
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abejgonzalez
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c49eef3224
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Small cleanup to CY DigitalTop | Move E300 configs to unique folder
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2020-09-07 15:26:30 -07:00 |
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abejgonzalez
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a8083aa570
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First pass at fpga-shells with IOBinders
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2020-09-07 11:48:27 -07:00 |
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abejgonzalez
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1fa1b6d57f
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Small makefile cleanup
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2020-09-04 19:03:26 -07:00 |
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abejgonzalez
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8eb807a2fd
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Use DigitalTop in Platform | Use Chipyard BootRom
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2020-09-04 18:56:32 -07:00 |
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James Dunn
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990362933d
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Simple makefile variable fix to allow make mcs
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2020-09-04 14:16:42 -07:00 |
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abejgonzalez
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5a885fdcfd
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Delete old makefiles | Full switch to CY make system
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2020-09-03 21:28:05 -07:00 |
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abejgonzalez
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0656c5da4f
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First pass on using CY make system
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2020-09-03 20:29:19 -07:00 |
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