Jerry Zhao
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a8766ea8fc
|
Precisely specify bus frequencies
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2023-10-31 14:25:16 -07:00 |
|
Jerry Zhao
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eb3a0aecf4
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Add PortAPI between IO and Harness blocks
|
2023-10-05 15:02:56 -07:00 |
|
Jerry Zhao
|
0b81a82459
|
Fix VCU118 freq adjustment configs
Resolves #1583
|
2023-09-06 10:55:53 -07:00 |
|
Jerry Zhao
|
078bce1323
|
Bump to chisel3.6
|
2023-07-05 10:32:55 -07:00 |
|
jerryho
|
9844deb172
|
using dp(ExtTLMem).get.master.beatBytes to obtain MemoryBus data width
|
2023-05-27 18:12:56 +08:00 |
|
jerryho
|
45eeee5092
|
fix the data field width mismatch between AXI that goes to MIG core and that of the Memory Bus
|
2023-05-26 16:08:59 +08:00 |
|
Jerry Zhao
|
57f5168408
|
Set number of idbits correctly for fpga ddr
|
2023-05-15 00:04:12 -07:00 |
|
Jerry Zhao
|
f4739be632
|
Update multi-chip API for harnesses
|
2023-05-15 00:03:22 -07:00 |
|
Jerry Zhao
|
2077e4304d
|
Explicitly provide refClockFreqMHz to harnessClockInstantiator
|
2023-05-13 11:18:03 -07:00 |
|
Jerry Zhao
|
b8e95e0305
|
Rename implicit clock/reset to referenceclock/reset
|
2023-05-12 15:11:44 -07:00 |
|
Jerry Zhao
|
607c2b5a73
|
Unify multi-node btw chipyard/firechip | unify harness clocking
|
2023-05-12 08:41:34 -07:00 |
|
Jerry Zhao
|
64ad77bbcf
|
Make FPGA flows use the harnessClockInstantiator
|
2023-05-11 15:04:04 -07:00 |
|
Jerry Zhao
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ac281daa78
|
Move TestHarness to chipyard.harness, make chipyard/harness directory
|
2023-05-08 08:00:56 -07:00 |
|
Jerry Zhao
|
df2e5ad9dc
|
Bump to latest rocket-chip/chisel3.5.6
|
2023-03-28 16:48:27 -07:00 |
|
Jerry Zhao
|
85fa9d1120
|
Add ARTY100t bringup + TSI-over-UART
|
2023-02-14 15:01:52 -08:00 |
|
abejgonzalez
|
292cc753ce
|
Run pre-commit on all files
|
2022-12-21 15:59:46 -08:00 |
|
Lori Li
|
0724431873
|
Clean up code
|
2022-11-30 16:56:09 +09:00 |
|
Jerry Zhao
|
f668ffdb03
|
Switch PRCI to HarnessBinder/IOBinders
|
2021-09-29 11:39:52 -07:00 |
|
Abraham Gonzalez
|
985faa4c8e
|
Small comment updates + cleanup
|
2021-04-03 12:55:27 -07:00 |
|
Abraham Gonzalez
|
be13781a1c
|
Set both MBUS/PBUS in configs | Add simple check for correct clocks
|
2021-04-02 16:43:59 -07:00 |
|
Abraham Gonzalez
|
5a41c5d9ac
|
Use multi-clock config. frags to determine VCU118 clk freq
|
2021-04-01 16:21:44 -07:00 |
|
abejgonzalez
|
09ef82cabf
|
Update harnessClk/Rst naming to buildtop | Small docs cleanup
|
2021-03-22 13:11:12 -07:00 |
|
abejgonzalez
|
9957538d38
|
Enable support for pullup R's on GPIOs
|
2021-02-25 13:54:53 -08:00 |
|
abejgonzalez
|
4d3ff26a73
|
Bump testchipip
|
2021-01-04 15:36:00 -08:00 |
|
abejgonzalez
|
f1fdab5bd3
|
Move TL mem switch frag to CY | Add require to not have TL/AXI backing mem
|
2020-11-23 16:58:34 -08:00 |
|
abejgonzalez
|
8f6de22e72
|
Fixed TinyRocketConfig | Small cleanup to VCU118/Arty configs
|
2020-11-23 16:30:39 -08:00 |
|
abejgonzalez
|
661a7701a7
|
Share DigitalTop/ChipyardSystem | Fix small naming compile error
|
2020-11-23 15:46:03 -08:00 |
|
abejgonzalez
|
d94a8efd43
|
Fix TLMemPort comment | Use Option instead of NoSimulator
|
2020-11-15 15:44:38 -08:00 |
|
abejgonzalez
|
c8add488ad
|
Reduce BOOM default freq. (play it safe)
|
2020-11-15 14:31:14 -08:00 |
|
abejgonzalez
|
55f19f79d3
|
Address fpga srcs
|
2020-11-12 15:39:29 -08:00 |
|
abejgonzalez
|
7ca3be236c
|
Bump bringup VCU118 | Ignore HTIF if no-debug module
|
2020-11-12 11:47:16 -08:00 |
|
abejgonzalez
|
082b230452
|
Add missing file
|
2020-11-08 17:51:21 -08:00 |
|
abejgonzalez
|
244205e2b4
|
Separate new sys_clk and ddr2 from TSI
|
2020-11-08 17:49:32 -08:00 |
|
Abraham Gonzalez
|
5a4cad0172
|
Merge pull request #6 from ucb-bar/local-fpga-support-docs
Local fpga support docs
|
2020-11-06 21:03:15 -08:00 |
|
abejgonzalez
|
c5e8fecb5c
|
Small renaming and cleanup
|
2020-11-06 21:00:18 -08:00 |
|
Abraham Gonzalez
|
9144e3c706
|
Fix pin mappings for TSI DDR
|
2020-11-06 20:51:11 -08:00 |
|
abejgonzalez
|
7baa1341ee
|
Use 2nd system clock for TSI DDR | Small cleanups
|
2020-11-06 16:34:45 -08:00 |
|
abejgonzalez
|
6aae66c54f
|
Add TSI Host Widget
|
2020-11-06 15:50:28 -08:00 |
|
Abraham Gonzalez
|
b0eed5075f
|
[temp] start integrating tsi host widget
|
2020-11-06 10:57:55 -08:00 |
|
abejgonzalez
|
84508bee6e
|
More FPGA prototyping docs
|
2020-11-05 21:51:25 -08:00 |
|
abejgonzalez
|
313fa4f129
|
Merge branch 'local-fpga-support' into local-fpga-support-docs
|
2020-11-05 21:24:03 -08:00 |
|
abejgonzalez
|
9a5b67bf8c
|
Use Chipyard configs as a base (VCU118)
|
2020-11-05 20:30:49 -08:00 |
|
abejgonzalez
|
255e88fe8f
|
Initial outline of FPGA prototyping docs
|
2020-11-05 17:06:34 -08:00 |
|
abejgonzalez
|
083f34ab23
|
Revert Chipyard system | Create new VCU118 Chipyard system
|
2020-11-05 15:44:54 -08:00 |
|
abejgonzalez
|
a7ab0dab59
|
Updated VCU118 | Bumped naming on Arty
|
2020-11-05 13:59:10 -08:00 |
|
Abraham Gonzalez
|
0eca51ba4d
|
Reorganize into bringup/simple | Bump sifive-blocks
|
2020-10-27 12:57:34 -07:00 |
|
Abraham Gonzalez
|
3c42e2cae7
|
Fixed BootROM | Updated HarnessBinders
|
2020-10-26 18:15:58 -07:00 |
|
Abraham Gonzalez
|
db73cab164
|
Add BootROM | Fix ResetWrangler for DDR | Add scripts
|
2020-10-20 21:20:11 -07:00 |
|
Abraham Gonzalez
|
dd358f45ab
|
UART Working... Bumped to newer fpga-shells
|
2020-10-19 11:29:25 -07:00 |
|
abejgonzalez
|
9ba4918cb8
|
Inject MMCDevice into TLSPI Node
|
2020-10-15 11:46:42 -07:00 |
|