Logo
Explore Help
Sign In
wu-arch/chipyard
Watch 1
Star 0
Fork 0
Code Issues Pull Requests Actions 28 Packages Projects Releases Wiki Activity
174 Commits 8 Branches 0 Tags
978832df9346ae4252211b7f2512a22dd0a09018
Commit Graph
7 Commits
Author SHA1 Message Date
abejgonzalez 2bd70937cb support verilator | rename build variable 2019-04-22 23:26:13 -07:00
abejgonzalez e4aa81b2f8 fix make clean 2019-04-18 14:25:37 -07:00
abejgonzalez 7d887b212c align rebar with tip of project-template master | fixes build issues 2019-04-17 16:02:44 -07:00
abejgonzalez c364869563 default to .gitignoring all files in verisim/vsim | read verilator.mk 2019-03-12 14:39:15 -07:00
abejgonzalez 2c246af110 rename makefiles | move verilog rule to common.mk 2019-03-12 14:39:15 -07:00
abejgonzalez 82273107c1 makefile changes/split | add scripts 2019-03-12 14:39:15 -07:00
alonamidandabejgonzalez 2def0dfea7 change dir structure 2019-03-12 14:30:38 -07:00
Powered by Gitea Version: 1.27.1 Page: 14ms Template: 2ms
Auto
English
Bahasa Indonesia Deutsch English Español Français Gaeilge Italiano Latviešu Magyar nyelv Nederlands Polski Português de Portugal Português do Brasil Suomi Svenska Türkçe Čeština Ελληνικά Български Русский Українська فارسی മലയാളം 日本語 简体中文 繁體中文(台灣) 繁體中文(香港) 한국어
Licenses API