Colin Schmidt
5fcae01825
Fix width of zeros after #74
2020-02-19 18:52:48 -08:00
Colin Schmidt
db0efd38fc
Fix CI tests
2020-02-19 17:23:10 -08:00
Abraham Gonzalez
ecc52b9b7c
add test case for we bug
2019-11-05 21:29:57 -08:00
Abraham Gonzalez
be3b05a909
add test case
2019-10-28 13:45:05 -07:00
Colin Schmidt
c23b2b6f84
SRAM depth to bigint
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max synflop depth support
Fix annotation mangling on the harness side
2019-05-14 10:10:47 -07:00
Colin Schmidt
0b9d74ada7
Fix unit tests update cost function once more
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bump mdf to master
2019-03-18 07:25:04 -07:00
edwardcwang
93bf7895be
Fix corner case in compiling a small mem using a large lib ( #32 )
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* Refactor bit pairs calculation into a separate function
* Minor clarifications
* Clarify MacroCompilerSpec helpers
* Add SmallTagArrayTest test
* Fix corner case in compiling a small mem using a large lib
2018-04-26 10:33:55 -07:00
edwardcwang
c884a2fb15
Correct multi-ported memory compilation ( #27 )
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* Correct multi-ported memory compilation
It was incorrectly splitting multiple times before. Fixed the issue and
added regression tests for this issue.
* Add 1 read 1 write test
2017-10-06 18:04:49 -07:00
Edward Wang
bc26f5eb1a
Address review comments
2017-10-03 11:56:30 -07:00
Edward Wang
5d3bebd2b9
Re-implement parallel mapping
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- Support byte-masked SRAM, yay
- Also nuke a bunch of bugs
2017-10-03 11:56:30 -07:00
Edward Wang
e89079f2d7
Test for non-empty Verilog
2017-10-03 11:56:30 -07:00
Edward Wang
df8b5815c6
Trim redundant MDF field
2017-10-03 11:56:30 -07:00
Edward Wang
a177c895e8
Finish rewriting in new format
2017-10-03 11:56:30 -07:00
