439 lines
14 KiB
Scala
439 lines
14 KiB
Scala
package barstools.macros
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import mdf.macrolib._
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// Specific one-off tests to run, not created by a generator.
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// Check that verilog actually gets generated.
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// TODO: check the actual verilog's correctness?
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class GenerateSomeVerilog extends MacroCompilerSpec with HasSRAMGenerator with HasSimpleDepthTestGenerator {
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override lazy val width = 32
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override lazy val memDepth = 2048
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override lazy val libDepth = 1024
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it should "execute fine" in {
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compileExecuteAndTest(mem, lib, v, output)
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}
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it should "generate non-empty verilog" in {
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val verilog = scala.io.Source.fromFile(vPrefix + "/" + v).getLines().mkString("\n")
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verilog.isEmpty shouldBe false
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}
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}
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class RocketChipTest extends MacroCompilerSpec with HasSRAMGenerator {
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val mem = s"mem-RocketChipTest.json"
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val lib = s"lib-RocketChipTest.json"
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val v = s"RocketChipTest.v"
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val libSRAMs = Seq(
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SRAMMacro(
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name="SRAM1RW1024x8",
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depth=1024,
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width=8,
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family="1rw",
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ports=Seq(
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generateReadWritePort("", 8, 1024)
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)
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),
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SRAMMacro(
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name="SRAM1RW512x32",
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depth=512,
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width=32,
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family="1rw",
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ports=Seq(
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generateReadWritePort("", 32, 512)
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)
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),
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SRAMMacro(
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name="SRAM1RW64x128",
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depth=64,
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width=128,
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family="1rw",
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ports=Seq(
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generateReadWritePort("", 128, 64)
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)
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),
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SRAMMacro(
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name="SRAM1RW64x32",
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depth=64,
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width=32,
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family="1rw",
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ports=Seq(
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generateReadWritePort("", 32, 64)
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)
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),
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SRAMMacro(
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name="SRAM1RW64x8",
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depth=64,
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width=8,
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family="1rw",
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ports=Seq(
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generateReadWritePort("", 8, 64)
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)
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),
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SRAMMacro(
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name="SRAM1RW512x8",
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depth=512,
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width=8,
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family="1rw",
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ports=Seq(
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generateReadWritePort("", 8, 512)
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)
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),
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SRAMMacro(
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name="SRAM2RW64x32",
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depth=64,
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width=32,
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family="1r1w",
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ports=Seq(
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generateReadPort("portA", 32, 64),
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generateWritePort("portB", 32, 64)
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)
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)
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)
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val memSRAMs = mdf.macrolib.Utils.readMDFFromString(
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"""
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[
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{
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"type": "sram",
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"name": "tag_array_ext",
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"depth": 64,
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"width": 80,
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"ports": [
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{
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"clock port name": "RW0_clk",
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"mask granularity": 20,
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"output port name": "RW0_rdata",
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"input port name": "RW0_wdata",
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"address port name": "RW0_addr",
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"mask port name": "RW0_wmask",
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"chip enable port name": "RW0_en",
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"write enable port name": "RW0_wmode"
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}
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]
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},
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{
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"type": "sram",
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"name": "T_1090_ext",
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"depth": 512,
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"width": 64,
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"ports": [
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{
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"clock port name": "RW0_clk",
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"output port name": "RW0_rdata",
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"input port name": "RW0_wdata",
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"address port name": "RW0_addr",
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"chip enable port name": "RW0_en",
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"write enable port name": "RW0_wmode"
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}
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]
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},
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{
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"type": "sram",
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"name": "T_406_ext",
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"depth": 512,
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"width": 64,
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"ports": [
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{
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"clock port name": "RW0_clk",
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"mask granularity": 8,
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"output port name": "RW0_rdata",
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"input port name": "RW0_wdata",
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"address port name": "RW0_addr",
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"mask port name": "RW0_wmask",
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"chip enable port name": "RW0_en",
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"write enable port name": "RW0_wmode"
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}
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]
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},
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{
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"type": "sram",
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"name": "T_2172_ext",
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"depth": 64,
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"width": 88,
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"ports": [
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{
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"clock port name": "W0_clk",
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"mask granularity": 22,
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"input port name": "W0_data",
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"address port name": "W0_addr",
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"chip enable port name": "W0_en",
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"mask port name": "W0_mask"
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},
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{
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"clock port name": "R0_clk",
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"output port name": "R0_data",
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"address port name": "R0_addr",
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"chip enable port name": "R0_en"
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}
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]
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}
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]
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""").getOrElse(List())
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writeToLib(lib, libSRAMs)
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writeToMem(mem, memSRAMs)
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val output = // TODO: check correctness...
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"""
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circuit T_2172_ext :
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module tag_array_ext :
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input RW0_clk : Clock
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input RW0_addr : UInt<6>
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input RW0_wdata : UInt<80>
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output RW0_rdata : UInt<80>
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input RW0_en : UInt<1>
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input RW0_wmode : UInt<1>
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input RW0_wmask : UInt<4>
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inst mem_0_0 of SRAM1RW64x8
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inst mem_0_1 of SRAM1RW64x8
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inst mem_0_2 of SRAM1RW64x8
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inst mem_0_3 of SRAM1RW64x8
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inst mem_0_4 of SRAM1RW64x8
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inst mem_0_5 of SRAM1RW64x8
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inst mem_0_6 of SRAM1RW64x8
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inst mem_0_7 of SRAM1RW64x8
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inst mem_0_8 of SRAM1RW64x8
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inst mem_0_9 of SRAM1RW64x8
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inst mem_0_10 of SRAM1RW64x8
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inst mem_0_11 of SRAM1RW64x8
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mem_0_0.clk <= RW0_clk
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mem_0_0.addr <= RW0_addr
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node RW0_rdata_0_0 = bits(mem_0_0.dout, 7, 0)
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mem_0_0.din <= bits(RW0_wdata, 7, 0)
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mem_0_0.write_en <= and(and(RW0_wmode, bits(RW0_wmask, 0, 0)), UInt<1>("h1"))
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mem_0_1.clk <= RW0_clk
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mem_0_1.addr <= RW0_addr
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node RW0_rdata_0_1 = bits(mem_0_1.dout, 7, 0)
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mem_0_1.din <= bits(RW0_wdata, 15, 8)
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mem_0_1.write_en <= and(and(RW0_wmode, bits(RW0_wmask, 0, 0)), UInt<1>("h1"))
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mem_0_2.clk <= RW0_clk
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mem_0_2.addr <= RW0_addr
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node RW0_rdata_0_2 = bits(mem_0_2.dout, 3, 0)
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mem_0_2.din <= bits(RW0_wdata, 19, 16)
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mem_0_2.write_en <= and(and(RW0_wmode, bits(RW0_wmask, 0, 0)), UInt<1>("h1"))
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mem_0_3.clk <= RW0_clk
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mem_0_3.addr <= RW0_addr
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node RW0_rdata_0_3 = bits(mem_0_3.dout, 7, 0)
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mem_0_3.din <= bits(RW0_wdata, 27, 20)
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mem_0_3.write_en <= and(and(RW0_wmode, bits(RW0_wmask, 1, 1)), UInt<1>("h1"))
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mem_0_4.clk <= RW0_clk
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mem_0_4.addr <= RW0_addr
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node RW0_rdata_0_4 = bits(mem_0_4.dout, 7, 0)
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mem_0_4.din <= bits(RW0_wdata, 35, 28)
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mem_0_4.write_en <= and(and(RW0_wmode, bits(RW0_wmask, 1, 1)), UInt<1>("h1"))
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mem_0_5.clk <= RW0_clk
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mem_0_5.addr <= RW0_addr
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node RW0_rdata_0_5 = bits(mem_0_5.dout, 3, 0)
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mem_0_5.din <= bits(RW0_wdata, 39, 36)
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mem_0_5.write_en <= and(and(RW0_wmode, bits(RW0_wmask, 1, 1)), UInt<1>("h1"))
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mem_0_6.clk <= RW0_clk
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mem_0_6.addr <= RW0_addr
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node RW0_rdata_0_6 = bits(mem_0_6.dout, 7, 0)
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mem_0_6.din <= bits(RW0_wdata, 47, 40)
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mem_0_6.write_en <= and(and(RW0_wmode, bits(RW0_wmask, 2, 2)), UInt<1>("h1"))
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mem_0_7.clk <= RW0_clk
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mem_0_7.addr <= RW0_addr
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node RW0_rdata_0_7 = bits(mem_0_7.dout, 7, 0)
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mem_0_7.din <= bits(RW0_wdata, 55, 48)
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mem_0_7.write_en <= and(and(RW0_wmode, bits(RW0_wmask, 2, 2)), UInt<1>("h1"))
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mem_0_8.clk <= RW0_clk
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mem_0_8.addr <= RW0_addr
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node RW0_rdata_0_8 = bits(mem_0_8.dout, 3, 0)
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mem_0_8.din <= bits(RW0_wdata, 59, 56)
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mem_0_8.write_en <= and(and(RW0_wmode, bits(RW0_wmask, 2, 2)), UInt<1>("h1"))
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mem_0_9.clk <= RW0_clk
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mem_0_9.addr <= RW0_addr
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node RW0_rdata_0_9 = bits(mem_0_9.dout, 7, 0)
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mem_0_9.din <= bits(RW0_wdata, 67, 60)
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mem_0_9.write_en <= and(and(RW0_wmode, bits(RW0_wmask, 3, 3)), UInt<1>("h1"))
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mem_0_10.clk <= RW0_clk
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mem_0_10.addr <= RW0_addr
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node RW0_rdata_0_10 = bits(mem_0_10.dout, 7, 0)
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mem_0_10.din <= bits(RW0_wdata, 75, 68)
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mem_0_10.write_en <= and(and(RW0_wmode, bits(RW0_wmask, 3, 3)), UInt<1>("h1"))
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mem_0_11.clk <= RW0_clk
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mem_0_11.addr <= RW0_addr
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node RW0_rdata_0_11 = bits(mem_0_11.dout, 3, 0)
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mem_0_11.din <= bits(RW0_wdata, 79, 76)
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mem_0_11.write_en <= and(and(RW0_wmode, bits(RW0_wmask, 3, 3)), UInt<1>("h1"))
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node RW0_rdata_0 = cat(RW0_rdata_0_11, cat(RW0_rdata_0_10, cat(RW0_rdata_0_9, cat(RW0_rdata_0_8, cat(RW0_rdata_0_7, cat(RW0_rdata_0_6, cat(RW0_rdata_0_5, cat(RW0_rdata_0_4, cat(RW0_rdata_0_3, cat(RW0_rdata_0_2, cat(RW0_rdata_0_1, RW0_rdata_0_0)))))))))))
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RW0_rdata <= mux(UInt<1>("h1"), RW0_rdata_0, UInt<1>("h0"))
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extmodule SRAM1RW64x8 :
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input clk : Clock
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input addr : UInt<6>
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input din : UInt<8>
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output dout : UInt<8>
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input write_en : UInt<1>
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defname = SRAM1RW64x8
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module T_1090_ext :
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input RW0_clk : Clock
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input RW0_addr : UInt<9>
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input RW0_wdata : UInt<64>
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output RW0_rdata : UInt<64>
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input RW0_en : UInt<1>
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input RW0_wmode : UInt<1>
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inst mem_0_0 of SRAM1RW512x32
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inst mem_0_1 of SRAM1RW512x32
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mem_0_0.clk <= RW0_clk
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mem_0_0.addr <= RW0_addr
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node RW0_rdata_0_0 = bits(mem_0_0.dout, 31, 0)
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mem_0_0.din <= bits(RW0_wdata, 31, 0)
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mem_0_0.write_en <= and(and(RW0_wmode, UInt<1>("h1")), UInt<1>("h1"))
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mem_0_1.clk <= RW0_clk
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mem_0_1.addr <= RW0_addr
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node RW0_rdata_0_1 = bits(mem_0_1.dout, 31, 0)
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mem_0_1.din <= bits(RW0_wdata, 63, 32)
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mem_0_1.write_en <= and(and(RW0_wmode, UInt<1>("h1")), UInt<1>("h1"))
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node RW0_rdata_0 = cat(RW0_rdata_0_1, RW0_rdata_0_0)
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RW0_rdata <= mux(UInt<1>("h1"), RW0_rdata_0, UInt<1>("h0"))
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extmodule SRAM1RW512x32 :
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input clk : Clock
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input addr : UInt<9>
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input din : UInt<32>
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output dout : UInt<32>
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input write_en : UInt<1>
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defname = SRAM1RW512x32
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module T_406_ext :
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input RW0_clk : Clock
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input RW0_addr : UInt<9>
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input RW0_wdata : UInt<64>
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output RW0_rdata : UInt<64>
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input RW0_en : UInt<1>
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input RW0_wmode : UInt<1>
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input RW0_wmask : UInt<8>
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inst mem_0_0 of SRAM1RW512x8
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inst mem_0_1 of SRAM1RW512x8
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inst mem_0_2 of SRAM1RW512x8
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inst mem_0_3 of SRAM1RW512x8
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inst mem_0_4 of SRAM1RW512x8
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inst mem_0_5 of SRAM1RW512x8
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inst mem_0_6 of SRAM1RW512x8
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inst mem_0_7 of SRAM1RW512x8
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mem_0_0.clk <= RW0_clk
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mem_0_0.addr <= RW0_addr
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node RW0_rdata_0_0 = bits(mem_0_0.dout, 7, 0)
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mem_0_0.din <= bits(RW0_wdata, 7, 0)
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mem_0_0.write_en <= and(and(RW0_wmode, bits(RW0_wmask, 0, 0)), UInt<1>("h1"))
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mem_0_1.clk <= RW0_clk
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mem_0_1.addr <= RW0_addr
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node RW0_rdata_0_1 = bits(mem_0_1.dout, 7, 0)
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mem_0_1.din <= bits(RW0_wdata, 15, 8)
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mem_0_1.write_en <= and(and(RW0_wmode, bits(RW0_wmask, 1, 1)), UInt<1>("h1"))
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mem_0_2.clk <= RW0_clk
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mem_0_2.addr <= RW0_addr
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node RW0_rdata_0_2 = bits(mem_0_2.dout, 7, 0)
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mem_0_2.din <= bits(RW0_wdata, 23, 16)
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mem_0_2.write_en <= and(and(RW0_wmode, bits(RW0_wmask, 2, 2)), UInt<1>("h1"))
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mem_0_3.clk <= RW0_clk
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mem_0_3.addr <= RW0_addr
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node RW0_rdata_0_3 = bits(mem_0_3.dout, 7, 0)
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mem_0_3.din <= bits(RW0_wdata, 31, 24)
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mem_0_3.write_en <= and(and(RW0_wmode, bits(RW0_wmask, 3, 3)), UInt<1>("h1"))
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mem_0_4.clk <= RW0_clk
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mem_0_4.addr <= RW0_addr
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node RW0_rdata_0_4 = bits(mem_0_4.dout, 7, 0)
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mem_0_4.din <= bits(RW0_wdata, 39, 32)
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mem_0_4.write_en <= and(and(RW0_wmode, bits(RW0_wmask, 4, 4)), UInt<1>("h1"))
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mem_0_5.clk <= RW0_clk
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mem_0_5.addr <= RW0_addr
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node RW0_rdata_0_5 = bits(mem_0_5.dout, 7, 0)
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mem_0_5.din <= bits(RW0_wdata, 47, 40)
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mem_0_5.write_en <= and(and(RW0_wmode, bits(RW0_wmask, 5, 5)), UInt<1>("h1"))
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mem_0_6.clk <= RW0_clk
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mem_0_6.addr <= RW0_addr
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node RW0_rdata_0_6 = bits(mem_0_6.dout, 7, 0)
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mem_0_6.din <= bits(RW0_wdata, 55, 48)
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mem_0_6.write_en <= and(and(RW0_wmode, bits(RW0_wmask, 6, 6)), UInt<1>("h1"))
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mem_0_7.clk <= RW0_clk
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mem_0_7.addr <= RW0_addr
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node RW0_rdata_0_7 = bits(mem_0_7.dout, 7, 0)
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mem_0_7.din <= bits(RW0_wdata, 63, 56)
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mem_0_7.write_en <= and(and(RW0_wmode, bits(RW0_wmask, 7, 7)), UInt<1>("h1"))
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node RW0_rdata_0 = cat(RW0_rdata_0_7, cat(RW0_rdata_0_6, cat(RW0_rdata_0_5, cat(RW0_rdata_0_4, cat(RW0_rdata_0_3, cat(RW0_rdata_0_2, cat(RW0_rdata_0_1, RW0_rdata_0_0)))))))
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RW0_rdata <= mux(UInt<1>("h1"), RW0_rdata_0, UInt<1>("h0"))
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extmodule SRAM1RW512x8 :
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input clk : Clock
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input addr : UInt<9>
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input din : UInt<8>
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output dout : UInt<8>
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input write_en : UInt<1>
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defname = SRAM1RW512x8
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module T_2172_ext :
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input W0_clk : Clock
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input W0_addr : UInt<6>
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input W0_data : UInt<88>
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input W0_en : UInt<1>
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input W0_mask : UInt<4>
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input R0_clk : Clock
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input R0_addr : UInt<6>
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output R0_data : UInt<88>
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input R0_en : UInt<1>
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inst mem_0_0 of SRAM2RW64x32
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inst mem_0_1 of SRAM2RW64x32
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inst mem_0_2 of SRAM2RW64x32
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inst mem_0_3 of SRAM2RW64x32
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mem_0_0.portB_clk <= W0_clk
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mem_0_0.portB_addr <= W0_addr
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mem_0_0.portB_din <= bits(W0_data, 21, 0)
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mem_0_0.portB_write_en <= and(and(UInt<1>("h1"), bits(W0_mask, 0, 0)), UInt<1>("h1"))
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mem_0_1.portB_clk <= W0_clk
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mem_0_1.portB_addr <= W0_addr
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mem_0_1.portB_din <= bits(W0_data, 43, 22)
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mem_0_1.portB_write_en <= and(and(UInt<1>("h1"), bits(W0_mask, 1, 1)), UInt<1>("h1"))
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mem_0_2.portB_clk <= W0_clk
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mem_0_2.portB_addr <= W0_addr
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mem_0_2.portB_din <= bits(W0_data, 65, 44)
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mem_0_2.portB_write_en <= and(and(UInt<1>("h1"), bits(W0_mask, 2, 2)), UInt<1>("h1"))
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mem_0_3.portB_clk <= W0_clk
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mem_0_3.portB_addr <= W0_addr
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mem_0_3.portB_din <= bits(W0_data, 87, 66)
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mem_0_3.portB_write_en <= and(and(UInt<1>("h1"), bits(W0_mask, 3, 3)), UInt<1>("h1"))
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mem_0_0.portA_clk <= R0_clk
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mem_0_0.portA_addr <= R0_addr
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node R0_data_0_0 = bits(mem_0_0.portA_dout, 21, 0)
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mem_0_1.portA_clk <= R0_clk
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mem_0_1.portA_addr <= R0_addr
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node R0_data_0_1 = bits(mem_0_1.portA_dout, 21, 0)
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mem_0_2.portA_clk <= R0_clk
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mem_0_2.portA_addr <= R0_addr
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node R0_data_0_2 = bits(mem_0_2.portA_dout, 21, 0)
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mem_0_3.portA_clk <= R0_clk
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mem_0_3.portA_addr <= R0_addr
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node R0_data_0_3 = bits(mem_0_3.portA_dout, 21, 0)
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node R0_data_0 = cat(R0_data_0_3, cat(R0_data_0_2, cat(R0_data_0_1, R0_data_0_0)))
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R0_data <= mux(UInt<1>("h1"), R0_data_0, UInt<1>("h0"))
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extmodule SRAM2RW64x32 :
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input portA_clk : Clock
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input portA_addr : UInt<6>
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output portA_dout : UInt<32>
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input portB_clk : Clock
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input portB_addr : UInt<6>
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input portB_din : UInt<32>
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input portB_write_en : UInt<1>
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defname = SRAM2RW64x32
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"""
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compileExecuteAndTest(mem, lib, v, output)
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}
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