Commit Graph

25 Commits

Author SHA1 Message Date
Jerry Zhao
56e1aeb400 Support FireSim diplomatic multiclock 2020-07-07 20:54:31 -07:00
David Biancolin
fa2d620fb2 Remove commented code in ScalaTests 2020-05-19 00:50:14 +00:00
David Biancolin
99846c1ccb [firechip] Use the standard Chipyard generator 2020-05-17 00:18:17 +00:00
Jerry Zhao
3f5a204fd0 BOOM Bump w. Fromajo (#523)
* [uart] add uart adapter | add uart + adapter to all configs

* [uart] change pty define name | add uart to all configs that need it

* [uart] default to 115200 baudrate

* [dromajo] first working commit

* [dromajo] bump boom for commit-width > 1 fix

* [dromajo] adjust dromajo commits

* [dromajo] bump boom

* commit dromajo changes

* extra

* [dromajo] add block device to configs

* rebump older modules

* bump firesim

* [chipyard] enable dromajo in midas level simulation

* [testchipip] forgot to bump

* get rid of breaking things

* bump firesim

* bump boom

* Bump BOOM to ifu3 WIP

* bump firesim

* fix how memory is passed to dromajo

* bump boom and firesim

* fix merge issues

* add dromajo cosim bridge in chipyard

* move traceio back into testchipip (#488)

* refer to testchipip traceio in firechip (#490)

* Move TraceIO fragment to chipyard (#492)

* fix chipyard dromajo bridge (#493)

* Sboom dromajo bump (#501)

* [FireChip] Use clock in BridgeBinders

* [firesim] Update TraceGen BridgeBinder

* [Firechip] Add support for Tile <-> Uncore rational division

* [firesim] Update the multiclock test

* [firechip] Commit some Eagle X-related mock configs

* [firechip] Instantiate multiple TracerV bridges

* [Firechip] Include reset in tracerv tokens

* [TracerV] Drop the first token in comparison tests

* [Firechip] Make reverse instruction order in trace printf

* WARNING: Point at a fork of boom @ davidbiancolin

* [firesim] Update ClockBridge API

* Add Gemmini to README [ci skip] (#487)

* [firechip] Isolate all firesim-multiclock stuff in a single file

* add documentation on ring network and system bus

* Bump firesim for CI

* Bump FireSim

* Bump testchipip to dev

[ci skip]

* Bump FireSim

* [make] split up specific make vars/targets into frags (#499)

* [make] split up specific make vars/targets into frags

* [make] move dramsim and max-cycles into SIM_FLAGS

* [misc] move ariane configs to configs/ folder

* [dromajo] add dromajo

* [dromajo] bump for new traceio changes

* bump firesim

* bump firesim

* point to chipyard traceio

* bump boom

Co-authored-by: David Biancolin <david.biancolin@gmail.com>
Co-authored-by: Howard Mao <zhehao.mao@gmail.com>

* Support Dromajo + TracerV configurations

* [docs] add documentation for Dromajo in FireSim + Chipyard

* add a bit more docs

* [docs] bump docs

* [firesim] dump artefacts in firesim

* [firesim] update firesim

* [testchipip] remove extraneous items in testchipip

* [dromajo] prevent dromajo from breaking when params unset

* update firesim, dromajo, and testchipip

* [firesim] bump firesim

* [firesim] bump firesim

* [misc] bump firesim and testchipip for reviewer comments

* remove WithNoGPIO fragment

* bump firesim

* bump dromajo boom config

* bump firesim

* generate artefacts in firesim testsuite

Co-authored-by: abejgonzalez <abe.j.gonza@gmail.com>
Co-authored-by: Abraham Gonzalez <abe.gonzalez@berkeley.edu>
Co-authored-by: David Biancolin <david.biancolin@gmail.com>
Co-authored-by: Howard Mao <zhehao.mao@gmail.com>
2020-05-16 00:21:24 -07:00
David Biancolin
6950ad7cee Comment out Ariane from ScalaTests 2020-05-12 22:01:14 +00:00
David Biancolin
b26ed91b73 [CI] Convert FireSim tests to use ScalaTest 2020-04-26 21:11:31 -07:00
David Biancolin
b303cf6e81 Rocket Chip Stage/Phase Bump (#503)
[WIP] Minimally elaborating design

Bring up a feature-complete Chipyard stage

Pull in Makefrag generation; Bump submodules

Update config generation, and global reset scheme

Bump submodules; clean up

Bump FireSim

Remove some unhygenic comments / WS

Remove the rocketchip subproject

[CI] Lengthen ariane tests timeout

Address some remaining reviewer comments

[firechip] Refresh a Field that cannot be used across repeated instantiations

Bump all submodules
2020-04-18 17:54:27 +00:00
David Biancolin
1b7158835a Bump firesim for CI 2020-03-24 10:43:01 -07:00
David Biancolin
7a17323bed [firechip] Isolate all firesim-multiclock stuff in a single file 2020-03-19 10:00:17 -07:00
David Biancolin
d80c2f7c08 Merge remote-tracking branch 'origin/dev' into firesim-multiclock
[ci skip]
2020-03-18 09:22:17 -07:00
David Biancolin
b47e692b4b [TracerV] Drop the first token in comparison tests 2020-01-20 12:55:47 -08:00
David Biancolin
924f440385 [Firechip] Include reset in tracerv tokens 2020-01-20 12:00:23 -08:00
David Biancolin
3fbc074b01 [firechip] Instantiate multiple TracerV bridges 2020-01-17 17:56:37 -08:00
David Biancolin
38834a99e1 [firesim] Update the multiclock test 2020-01-09 16:51:27 -08:00
David Biancolin
bcddd6e0f6 [Firechip] Add support for Tile <-> Uncore rational division 2019-11-22 16:29:55 -08:00
Howard Mao
05af2f9a9c Fix tracegen target and add to CI 2019-10-21 09:55:40 -07:00
Abraham Gonzalez
526da162dd update scala test suite 2019-10-10 18:27:02 +00:00
David Biancolin
53f58f6baa Support serializable endpoints; Golden Gate stage 2019-10-04 14:54:26 -07:00
David Biancolin
7c0bb51242 [firechip] Update scalatest suite 2019-10-04 18:16:14 +00:00
David Biancolin
5845862525 [Firechip] Push FASED configs into TargetConfigs.scala 2019-10-04 18:16:14 +00:00
David Biancolin
868c2b3b6d [firechip] Make some TracerV tests less strict 2019-09-26 20:49:50 +00:00
David Biancolin
38588b67ef Bump FireSim, update reset delay in ScalaTests 2019-09-19 15:21:08 -07:00
David Biancolin
270e558272 Initial MIDAS2 support 2019-07-23 22:04:12 +00:00
David Biancolin
2a58f387ed Fix some test suite handling 2019-05-28 01:50:39 +00:00
David Biancolin
c0d4e848ba WIP 2019-05-27 22:53:05 +00:00