 David Biancolin
|
67145c6ccd
|
[clocking] Fix FireSim clock look up
|
2020-09-25 10:05:28 -07:00 |
|
|
David Biancolin
|
1b3514f95f
|
[clocks] Specify a default frequency for TraceGen
|
2020-09-25 10:03:46 -07:00 |
|
|
David Biancolin
|
7b8a954d04
|
[firechip] Rework FireSim clocking to be more similar to default CY targets
|
2020-09-24 23:32:07 -07:00 |
|
|
David Biancolin
|
cc949aadab
|
[clocking] Address some of Colin's PR comments
|
2020-09-24 23:28:47 -07:00 |
|
|
David Biancolin
|
f6989a1968
|
[clocks] Use the periphery frequency as the default
|
2020-09-24 23:24:08 -07:00 |
|
|
David Biancolin
|
96bf702c3b
|
[clocks] Factor out the PLL calculations into their own class
|
2020-09-24 23:23:11 -07:00 |
|
|
Zitao Fang
|
6641c1f983
|
Attempt to fix CI
|
2020-09-24 22:42:49 -07:00 |
|
|
David Biancolin
|
84195d28bb
|
[clocks] Don't override existing take frequency if present.
|
2020-09-23 15:29:52 -07:00 |
|
|
Jerry ZhaoandGitHub
|
023d8096a9
|
Merge pull request #677 from ucb-bar/smartelf2hex-fix
Fix smartelf2hex.sh creating files 64x the minimum size
|
2020-09-22 17:04:45 -07:00 |
|
|
Jerry Zhao
|
d5660c01f3
|
Bump esp-isa-sim for loadmem-fix add TLS segments to smartelf2hex
|
2020-09-22 12:58:34 -07:00 |
|
|
Jerry ZhaoandGitHub
|
6c297e3179
|
Fix smartelf2hex.sh creating files 64x the minimum size
|
2020-09-22 11:08:52 -07:00 |
|
|
Zitao Fang
|
ae5fb8470b
|
Remove unnecessary CI tests
|
2020-09-19 10:27:20 -07:00 |
|
|
Zitao Fang
|
a02700a1d4
|
Add documentation for sodor
|
2020-09-18 23:14:47 -07:00 |
|
|
Zitao Fang
|
56d1d5b500
|
Fix CI errors
|
2020-09-18 22:42:19 -07:00 |
|
|
Zitao Fang
|
0c8771c35e
|
Merge branch 'dev' of github.com:ucb-bar/chipyard into sodor-integrate
|
2020-09-18 22:33:42 -07:00 |
|
|
Zitao Fang
|
a43400acb9
|
Update CI
|
2020-09-18 15:36:33 -07:00 |
|
|
Jerry ZhaoandGitHub
|
ba05b32f9c
|
Merge pull request #673 from ucb-bar/serial-tl
Serial-tilelink backing memory
|
2020-09-18 15:30:04 -07:00 |
|
|
David Biancolin
|
f36183d236
|
[clocks] Update AssignerKey name and comment
|
2020-09-18 11:28:31 -07:00 |
|
|
Jerry Zhao
|
bbf941c865
|
Bump Firesim
|
2020-09-18 10:43:58 -07:00 |
|
|
Jerry Zhao
|
aa355c7c1a
|
Bump firesim
|
2020-09-18 10:41:59 -07:00 |
|
|
Jerry Zhao
|
b9622c5132
|
Merge remote-tracking branch 'origin/dev' into serial-tl
|
2020-09-18 01:00:13 -07:00 |
|
|
James Dunn
|
9135cda959
|
Bypassing AON for system.reset. Using reset_core in ArtyShell test harness, which is derived from Xilinx reset IP block's mb_reset. Changing dutReset to same reset_core.
|
2020-09-17 13:43:28 -07:00 |
|
|
David Biancolin
|
ad147ec7f2
|
[clocks] Remove dealiaser and node injector until they are needed
|
2020-09-17 11:43:39 -07:00 |
|
|
David Biancolin
|
0f33ea3999
|
[clocks] Stringly specified clock frequencies; DRY out schemes
|
2020-09-17 11:41:05 -07:00 |
|
|
David Biancolin
|
6a26a350ee
|
[clocks] Update dealiaser based on feedback
|
2020-09-17 11:33:26 -07:00 |
|
|
David Biancolin
|
cfa7e30d95
|
[clocks] Fix comment in ClockDividerN
|
2020-09-17 11:32:51 -07:00 |
|
|
Jerry ZhaoandGitHub
|
43f746edb6
|
Merge pull request #675 from ucb-bar/faster-ci
Improve CI build times by grouping similar builds
|
2020-09-16 22:55:27 -07:00 |
|
|
David Biancolin
|
b8d3e4a66d
|
Update Idealized PLL config
|
2020-09-16 16:30:25 -07:00 |
|
|
David Biancolin
|
8e4dedcecf
|
Remove require guard on divided configs
|
2020-09-16 16:30:00 -07:00 |
|
|
David Biancolin
|
895bacea98
|
WIP - Simple divider-only PLL generation flow
|
2020-09-16 16:00:26 -07:00 |
|
|
Jerry Zhao
|
6874308981
|
Address review comments
|
2020-09-16 15:43:25 -07:00 |
|
|
Jerry Zhao
|
269af01a70
|
Bump testchipip
|
2020-09-16 13:51:33 -07:00 |
|
|
Jerry Zhao
|
36ccb12560
|
Bump testchipip
|
2020-09-16 10:29:03 -07:00 |
|
|
Jerry Zhao
|
aa8b7c15ec
|
Reduce CI redundancy by grouping builds
|
2020-09-16 00:57:05 -07:00 |
|
|
abejgonzalez
|
f1b40d51af
|
Connected clocks | Exposed Master TL port
|
2020-09-15 12:58:58 -07:00 |
|
|
Zitao Fang
|
1543acfacd
|
Merge branch 'dev' of github.com:ucb-bar/chipyard into sodor-integrate
|
2020-09-14 23:55:05 -07:00 |
|
|
Zitao Fang
|
642441e0a2
|
Replaced memory and fixed 3-stage single port arbiter
|
2020-09-14 23:54:52 -07:00 |
|
|
Jerry Zhao
|
0d8e87126c
|
Deprecate support for on-chip SerialAdapter
|
2020-09-14 19:43:32 -07:00 |
|
|
Jerry Zhao
|
f9cc1dc2c2
|
Merge remote-tracking branch 'origin/dev' into serial-tl
|
2020-09-14 19:35:43 -07:00 |
|
|
Jerry ZhaoandGitHub
|
23a199eccf
|
Merge pull request #674 from ucb-bar/iocells-fix
Undo regression in iocells flexibility
|
2020-09-14 19:32:37 -07:00 |
|
|
Jerry Zhao
|
10625a3a6c
|
Undo regression in iocells flexibility
|
2020-09-14 13:27:31 -07:00 |
|
|
Jerry ZhaoandGitHub
|
16c80112a7
|
Merge pull request #670 from ucb-bar/harness-refactor
Split IOBinders into IOBinders and HarnessBinders | punch out clocks to harness for simwidgets and bridges
|
2020-09-14 12:45:46 -07:00 |
|
|
Zitao Fang
|
5506f77679
|
Add CircleCI check and update Sodor config
|
2020-09-14 09:14:57 -07:00 |
|
|
abejgonzalez
|
72c0f4b3d3
|
Add GPIO Overlay
|
2020-09-13 16:37:20 -07:00 |
|
|
Jerry Zhao
|
6c5bce5430
|
Support Tilelink over serial
|
2020-09-13 11:59:16 -07:00 |
|
|
Jerry Zhao
|
be0c041232
|
Bump Firesim
|
2020-09-13 06:36:37 +00:00 |
|
|
Jerry Zhao
|
d2b42cee2c
|
Bump testchipip
|
2020-09-12 23:31:54 -07:00 |
|
|
abejgonzalez
|
69bf39bf13
|
Added more overlays | Closer to bringup platform
|
2020-09-12 18:18:13 -07:00 |
|
|
abejgonzalez
|
382e5f1ae8
|
Add forgotten file
|
2020-09-11 17:02:22 -07:00 |
|
|
abejgonzalez
|
e98a0f172f
|
Connected UART nicely
|
2020-09-11 16:55:25 -07:00 |
|