Jerry Zhao
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c7586be0c5
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Merge pull request #629 from ucb-bar/random-seed
Add RANDOM_SEED variable to set random init for VCS and Verilator simulations
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2020-08-03 14:46:16 -07:00 |
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Howard Mao
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d7f3f91f18
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implement fast loadmem feature
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2020-08-01 15:04:18 -07:00 |
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Zitao Fang
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a2bd26b91c
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Finished Sodor Design
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2020-07-31 20:54:42 -07:00 |
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ssteffl
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2e3b871beb
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Merge pull request #636 from ucb-bar/openroad
updated openroad hash
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2020-07-31 11:57:56 -07:00 |
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Sam Steffl
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16d4186ea4
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updated openroad hash
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2020-07-31 10:29:53 -07:00 |
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ssteffl
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88fceafb68
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Merge pull request #608 from ucb-bar/openroad
OpenROAD complete backend with nangate45
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2020-07-30 16:27:10 -07:00 |
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Zitao Fang
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98ef89cbde
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Created Internal Tiles
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2020-07-29 15:02:33 -07:00 |
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Zitao Fang
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6131ab58e5
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Connect cores
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2020-07-28 13:37:07 -07:00 |
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Zitao Fang
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14e2a9dbd1
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Fixed tile_master
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2020-07-24 14:17:29 -07:00 |
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Zitao Fang
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d56df6252c
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Sync
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2020-07-23 19:24:44 -07:00 |
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Nathan Pemberton
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29c924d45a
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Merge pull request #633 from ucb-bar/opensbi
Opensbi
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2020-07-22 10:00:47 -07:00 |
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Nathan Pemberton
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df07790a5a
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Bump FireMarshal/QEMU/riscv-isa-sim for OpenSBI
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2020-07-21 18:43:14 -07:00 |
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Jerry Zhao
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fdfef878af
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Merge branch 'dev' into diplomatic-clocks
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2020-07-21 11:21:51 -07:00 |
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Jerry Zhao
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b719919934
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Add RANDOM_SEED variable to set random init for VCS and Verilator simulations
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2020-07-20 18:25:18 -07:00 |
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Fang, Zitao
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11c1e87638
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Merge pull request #615 from ucb-bar/custom-core-doc
Documentation for Third-Party Core Integration
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2020-07-20 11:56:56 -07:00 |
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Zitao Fang
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692b120b65
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Fixed typo
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2020-07-19 21:48:07 -07:00 |
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Zitao Fang
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0a39819f44
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Add source file note
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2020-07-19 21:46:32 -07:00 |
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Zitao Fang
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2c7e7f3199
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Fixed file links
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2020-07-19 21:36:50 -07:00 |
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banahogg
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ae1e44a9e3
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Update BOOM URL in README.md
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2020-07-18 17:44:52 -07:00 |
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Zitao Fang
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fddf218147
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5th revision
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2020-07-16 15:39:07 -07:00 |
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Zitao Fang
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7bb1a48b1a
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Connect TileLink nodes
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2020-07-16 14:12:29 -07:00 |
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Jerry Zhao
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862d1fb774
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Merge pull request #627 from ucb-bar/firrtl-logging
Add variable to control FIRRTL logging verbosity
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2020-07-16 13:45:57 -07:00 |
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Zitao Fang
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97b8c3035c
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Merge branch 'dev' of github.com:ucb-bar/chipyard into custom-core-doc
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2020-07-15 11:15:46 -07:00 |
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Zitao Fang
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9fbc0a5bea
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Add links
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2020-07-15 11:08:36 -07:00 |
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Zitao Fang
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7ea464dc90
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4th revision
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2020-07-14 12:49:36 -07:00 |
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Zitao Fang
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1933fd8cbe
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Update sodor package structure
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2020-07-14 12:10:12 -07:00 |
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Zitao Fang
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14399e88b3
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Minor change
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2020-07-12 01:23:34 -07:00 |
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Zitao Fang
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ced7ea634c
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3rd Revision
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2020-07-12 01:08:13 -07:00 |
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David Biancolin
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d5a2d43f85
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Merge pull request #612 from ucb-bar/zynq-target
[firechip] Add a small target that should fit on all hosts
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2020-07-10 18:12:34 -07:00 |
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Albert Ou
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fbc71d4215
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Merge pull request #625 from ucb-bar/uart
Override default baud rate for FireChip
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2020-07-10 10:55:50 -07:00 |
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Jerry Zhao
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f8c9b316e2
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Merge pull request #620 from ucb-bar/simple_configs
Deduplicate across Chipyard configs into a ChipyardBaseConfig
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2020-07-09 17:12:19 -07:00 |
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Jerry Zhao
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2196a621c6
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Pass FIRRTL_LOGLEVEL to GenerateTopAndHarness
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2020-07-09 12:39:17 -07:00 |
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Jerry Zhao
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8124ce3df1
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Add FIRRTL_LOGLEVEL variable
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2020-07-09 12:38:21 -07:00 |
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Jerry Zhao
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7239e23185
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Merge branch 'dev' into simple_configs
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2020-07-09 11:31:33 -07:00 |
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Jerry Zhao
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11c87777fe
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Remove BOOM debug print
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2020-07-09 11:29:58 -07:00 |
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Albert Ou
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84620e027b
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Merge pull request #626 from ucb-bar/testchipip
Bump testchipip for bug fixes
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2020-07-08 23:01:35 -07:00 |
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Zitao Fang
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9ad9d00a23
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Second revision
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2020-07-08 16:02:31 -07:00 |
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Zitao Fang
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85069387c9
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Base Scratchpad
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2020-07-08 14:45:12 -07:00 |
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Albert Ou
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763ba42b4c
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Bump testchipip for FDT alignment and minLatency fixes
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2020-07-08 12:36:09 -07:00 |
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Albert Ou
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b55e579c91
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Override default baud rate for FireChip
This avoids target software needing to explicitly set the divisor to
match the UART bridge.
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2020-07-07 23:00:14 -07:00 |
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Jerry Zhao
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56e1aeb400
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Support FireSim diplomatic multiclock
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2020-07-07 20:54:31 -07:00 |
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Fang, Zitao
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60f7ec60bd
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Merge pull request #588 from ucb-bar/ariane-decouple
Test Suite Simplification
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2020-07-07 12:55:52 -07:00 |
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Jerry Zhao
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c023cf0688
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Rough initial implementation of diplomatic multiclock
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2020-07-06 22:01:26 -07:00 |
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alonamid
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19152d3b73
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Update README.md (#619)
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2020-07-06 20:29:34 -07:00 |
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Jerry Zhao
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661038f992
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Deduplicate across Chiypard configs into a ChipyardBaseConfig
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2020-07-06 17:54:24 -07:00 |
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Zitao Fang
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6cb8a60a80
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Remove Key List
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2020-07-05 21:18:31 -07:00 |
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Zitao Fang
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744e73fa92
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Editing Docs
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2020-07-05 21:05:21 -07:00 |
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Jerry Zhao
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d3721bbd99
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Merge pull request #618 from ucb-bar/mmio_fix
Fixes for AXI4 MMIO and FBus ports
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2020-07-03 12:15:50 -07:00 |
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Jerry Zhao
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a7047c4ba2
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Fix FireChip BridgeBinders
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2020-07-03 08:33:10 -07:00 |
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Zitao Fang
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104c350a59
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Custom Core Integration Doc, 1st Revision
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2020-07-02 15:56:15 -07:00 |
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