Cores now have an extra CoreParam, useSupervisor which was set to
the default false. Whether a core has supervisor mode is the union
of this and useVM which defaults true so not change was made by this
addition.
BusTopologies are now set with the Config system rather than a system
mixin and so all configs now include the config most similar to the
previous mixin
Testchipip was updated to be able to replace the systembus, in this
new config system, with a ring bus.
The L2 cache repo needed a similar update on how to find the buses.
It currently points to the ucb-bar fork
Treadle is bumped to its release branch
[WIP] Minimally elaborating design
Bring up a feature-complete Chipyard stage
Pull in Makefrag generation; Bump submodules
Update config generation, and global reset scheme
Bump submodules; clean up
Bump FireSim
Remove some unhygenic comments / WS
Remove the rocketchip subproject
[CI] Lengthen ariane tests timeout
Address some remaining reviewer comments
[firechip] Refresh a Field that cannot be used across repeated instantiations
Bump all submodules
* [make] split up specific make vars/targets into frags
* [make] move dramsim and max-cycles into SIM_FLAGS
* [misc] move ariane configs to configs/ folder
* Bump all submodules for chisel 3.2.0 and rocket-chip august-2019
* Fix subprojects that aren't tested from normal sims
* Fix firechip for chisel 3.2.0 and rc bump
* Bump boom for bug fix rebase
* [sbt] Don't rely on target-rtl symlink when FireSim is top [no ci]
* Bump boom for rc bump fix to bug fix
* Bump FireSim for CI check
* Bump FireSim
* Bump submodules after merge
