Tingyuan LIANG
d06abdb419
Swap two arguments to resolve bug
...
**Related issue**: N/A
**Type of change**: bug fix
**Impact**: other
**Release Notes**
The string of path for "-ip-vivado-tcls" could be empty ("")
For example, run "make SUB_PROJECT=arty bitstream" will get errors due the argument parsing in [prologue.tcl](d4b3878e4f/xilinx/common/tcl/prologue.tcl
2021-08-12 23:22:41 +08:00
abejgonzalez
16cdc88c52
Small comment + org. fix | Remove extra mkdirs
2021-05-12 16:42:05 -07:00
abejgonzalez
2874c98802
Add sim_files.f to fpga
2021-05-06 22:11:58 -07:00
abejgonzalez
1b4826ad82
Generalize debug-bitstream
2020-11-12 16:20:22 -08:00
abejgonzalez
d4d989ce0f
Rename make target to bitstream | Delete unused make stuff / tcl
2020-11-12 15:41:05 -08:00
abejgonzalez
a281869041
Fix Arty merge and errors from CY bump
2020-11-05 15:04:44 -08:00
abejgonzalez
356fa70c3c
Update fpga-shells submodule | Fix Arty Makefile lines
2020-11-05 11:16:17 -08:00
Abraham Gonzalez
0eca51ba4d
Reorganize into bringup/simple | Bump sifive-blocks
2020-10-27 12:57:34 -07:00
Abraham Gonzalez
db73cab164
Add BootROM | Fix ResetWrangler for DDR | Add scripts
2020-10-20 21:20:11 -07:00
Abraham Gonzalez
dd358f45ab
UART Working... Bumped to newer fpga-shells
2020-10-19 11:29:25 -07:00
abejgonzalez
7f387a254b
Working up until the MMC attachment
2020-10-14 23:09:49 -07:00
abejgonzalez
dcac9b79df
Basic working with UART
2020-10-14 16:15:10 -07:00
abejgonzalez
e98a0f172f
Connected UART nicely
2020-09-11 16:55:25 -07:00
abejgonzalez
56eead4053
NOT WORKING: VCU118 Commit
2020-09-08 17:04:56 -07:00
abejgonzalez
c49eef3224
Small cleanup to CY DigitalTop | Move E300 configs to unique folder
2020-09-07 15:26:30 -07:00
abejgonzalez
a8083aa570
First pass at fpga-shells with IOBinders
2020-09-07 11:48:27 -07:00
abejgonzalez
1fa1b6d57f
Small makefile cleanup
2020-09-04 19:03:26 -07:00
abejgonzalez
8eb807a2fd
Use DigitalTop in Platform | Use Chipyard BootRom
2020-09-04 18:56:32 -07:00
James Dunn
990362933d
Simple makefile variable fix to allow make mcs
2020-09-04 14:16:42 -07:00
abejgonzalez
5a885fdcfd
Delete old makefiles | Full switch to CY make system
2020-09-03 21:28:05 -07:00
abejgonzalez
0656c5da4f
First pass on using CY make system
2020-09-03 20:29:19 -07:00
