Jerry Zhao
30ac9dc2c8
Merge remote-tracking branch 'origin/main' into tcip-bump
2023-12-14 10:58:57 -08:00
Abraham Gonzalez
4132296831
Update TargetConfigs.scala
2023-11-15 16:49:19 -08:00
Jerry Zhao
a8766ea8fc
Precisely specify bus frequencies
2023-10-31 14:25:16 -07:00
Jerry Zhao
d83f395738
Update firechip for new testchipip
2023-10-24 18:42:27 -07:00
Jerry Zhao
3cbcf6b6e8
Fix TSIBridge loadmem param
2023-10-11 15:01:39 -07:00
Jerry Zhao
b949324d5a
Fix FireSim UARTBridge
2023-10-06 17:55:14 -07:00
Jerry Zhao
e6203bb25c
Fix fsim supernode memmodel
2023-10-05 23:56:29 -07:00
Jerry Zhao
eb3a0aecf4
Add PortAPI between IO and Harness blocks
2023-10-05 15:02:56 -07:00
Jerry Zhao
57ee757016
Remove MultiClockHarnessAXIMem
...
Previously, the MultiClockHarnessAXIMem stuff attached SimDRAM over the serial-tl link.
This was done to enable test-chip-like simulations, where the HarnessBinder/BridgeBinder
would effectively implement a similar system as what would go on the bringup platform.
Now that multi-chip-tops are supported, and co-simulation of the ChipTop and the BringupTop
are supported, we can remove all this old Harness-level stuff to reduce duplication
2023-09-16 09:47:47 -07:00
abejgonzalez
a48746f113
Deprecate Dromajo in FireSim, use cospike
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Move Cospike to testchipip
2023-08-30 17:55:04 -07:00
Jerry Zhao
563897ba22
Add WithUARTInitBaud/fix firesim uart configs
2023-06-19 06:03:56 -07:00
Jerry Zhao
1e3d4aad46
Update WithBackingScratchpad for firechip
2023-06-09 00:06:30 -07:00
Jerry Zhao
2f2cb1ac8b
Fix firesim clockgen to auto-generated the reference pll clock if not requested
2023-05-27 11:16:18 -07:00
Jerry Zhao
3f06dbc280
Fix clock group combiner behavior for rational-tile clocks
2023-05-26 17:50:55 -07:00
Jerry Zhao
f73951ac7f
Add TestChipConfigTweaks to model 2/1 tile/uncore division
2023-05-26 11:56:58 -07:00
Jerry Zhao
b69bcffc91
Merge remote-tracking branch 'origin/main' into unify
2023-05-19 11:28:52 -07:00
Jerry Zhao
f4739be632
Update multi-chip API for harnesses
2023-05-15 00:03:22 -07:00
Jerry Zhao
d4d81f7d22
Rename serialManagerParams -> serialTLManagerParams
2023-05-13 19:25:14 -07:00
Jerry Zhao
3330c23193
Support uni-directional TLSerdesser
2023-05-13 14:14:38 -07:00
Jerry Zhao
2077e4304d
Explicitly provide refClockFreqMHz to harnessClockInstantiator
2023-05-13 11:18:03 -07:00
Jerry Zhao
b8e95e0305
Rename implicit clock/reset to referenceclock/reset
2023-05-12 15:11:44 -07:00
Jerry Zhao
94d471bd9a
Set firesim harnessbinder freq to 1000 MHz by default
2023-05-12 14:44:07 -07:00
Jerry Zhao
607c2b5a73
Unify multi-node btw chipyard/firechip | unify harness clocking
2023-05-12 08:41:34 -07:00
Jerry Zhao
fbfb518b72
Merge remote-tracking branch 'origin/main' into renameserial
2023-05-10 11:39:11 -07:00
Sagar Karandikar
1c10f75622
Merge pull request #1471 from ucb-bar/lowmem-configs
...
Add 1GB / 4GB DRAM firechip configs for FireSim VCU118
2023-05-10 11:32:01 -07:00
Sagar Karandikar
abe8a7fb8b
remove extra newlines
2023-05-10 11:31:05 -07:00
Jerry Zhao
eced8e63d9
Rename SerialAdapter+SimSerial to TSIToTileLink/SimTSI/TSIHarness
2023-05-08 18:19:18 -07:00
Sagar Karandikar
95da9cefb5
4GB DRAM configs
2023-05-08 13:41:51 -07:00
Jerry Zhao
ac281daa78
Move TestHarness to chipyard.harness, make chipyard/harness directory
2023-05-08 08:00:56 -07:00
Jerry Zhao
4f5bbdca97
Flip serial_tl.clock for firechip BridgeBinders
2023-05-07 22:22:37 -07:00
Sagar Karandikar
40d0a1f3bd
low mem configs
2023-05-07 11:47:14 -07:00
Jerry Zhao
df2e5ad9dc
Bump to latest rocket-chip/chisel3.5.6
2023-03-28 16:48:27 -07:00
Sagar Karandikar
c14d11faac
lean gemmini tutorial ( #1413 )
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* lean gemmini tutorial
* bump firesim
* Update check-commit.sh
2023-03-22 20:26:26 -07:00
abejgonzalez
f4124e4cb6
Add Lean Gemmini FireChip target
2023-03-11 22:31:36 -08:00
abejgonzalez
a62c1f5010
Add a frag./config for MMIO only bridges
2023-03-09 20:09:46 -08:00
Jerry Zhao
9e7cdb6ccd
Remove Ringbus config from firechip
2023-02-11 15:48:16 -08:00
Jerry Zhao
41fd20a11e
Merge pull request #1303 from ucb-bar/ultrabump
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Bump to scala 2.13.10/chisel 3.5.5/latest rocketchip
2023-02-01 18:10:38 -08:00
Nandor Licker
6fbdacbd8b
Removed FireSim tests and harnesses ( #1317 )
...
These tests were moved to FireSim itself. This PR removes them from Chipyard.
2023-01-31 09:46:59 -08:00
Jerry Zhao
7780ed23bf
Bump to scala 2.13.10/chisel 3.5.5/latest rocketchip
2023-01-26 00:12:28 -08:00
Tushar Sondhi
95f30d0411
add more minimal firesim configs for testing ( #1313 )
2023-01-19 14:02:47 -08:00
tsondhi
ace6c7f490
add minimal firesim configs for testing fpga sims
2023-01-04 23:21:34 +00:00
Jerry Zhao
04e80a6984
Bump rocketchip to latest, chisel to 3.5.2
...
Remove fork of BusTopologies from rocket-chip
Update generators/chipyard/src/main/scala/config/AbstractConfig.scala
Co-authored-by: Abraham Gonzalez <abe.j.gonza@gmail.com >
2022-09-16 15:17:30 -07:00
Sagar Karandikar
8c56a5fe3c
Merge pull request #1172 from ucb-bar/firesim-no-mem
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firesim: Add a config with no mem port
2022-06-15 11:55:07 -07:00
David Biancolin
26dc18e878
firesim: Add a config with no mem port
2022-06-09 08:28:20 -07:00
Jerry Zhao
f8d83dddf5
Increase default SerialTL width to 32 ( #1040 )
2021-11-12 12:23:48 -08:00
Jerry Zhao
f668ffdb03
Switch PRCI to HarnessBinder/IOBinders
2021-09-29 11:39:52 -07:00
David Biancolin
580d311059
Use ResetPulseBridge + GlobalResetCondition; bump FireSim
2021-09-11 01:36:02 +00:00
alonamid
76b747dc84
Merge pull request #836 from ucb-bar/firesim-default-freqs
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Sane FireSim Default Target Freqs
2021-06-08 14:33:57 -07:00
alonamid
610adfc3f7
address PR review comments
2021-06-03 22:23:17 -07:00
alonamid
f2b56072a1
remove crossings in single clock domain
2021-06-02 21:26:29 -07:00
