 -T.K.-andGitHub
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0ba5c62b30
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FIX: fix scratchpad description
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2023-12-29 16:15:59 -08:00 |
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-T.K.-
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81fd8edb06
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ADD: add scratchpad
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2023-12-29 15:35:35 -08:00 |
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-T.K.-andGitHub
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fc4d54cffe
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Merge branch 'main' into arty100tfeatures
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2023-12-29 00:02:34 -08:00 |
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Jerry Zhao
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77c3b65fc9
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Don't punch out uart2tsi debug io
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2023-12-26 09:39:08 -08:00 |
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Jerry ZhaoandGitHub
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6730f55aa0
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Merge pull request #1710 from ucb-bar/organize_tcip
Update testchipip imports with new testchipip organization
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2023-12-21 12:33:11 -08:00 |
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-T.K.-andGitHub
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2be3d3d880
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Merge branch 'main' into fix-vcu118
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2023-12-20 22:40:45 -08:00 |
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-T.K.-
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c32de04b5d
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ADD: add inline docs
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2023-12-20 22:25:05 -08:00 |
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-T.K.-
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516ecf9d9e
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ADD: increase frequency to maximum
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2023-12-20 22:16:15 -08:00 |
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Jerry Zhao
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902d33ebd1
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Add Arty100T JTAG
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2023-12-20 08:43:35 -08:00 |
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Jerry Zhao
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81a2857ec7
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Add arty100t harness binder to map UART to PMOD JD
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2023-12-19 15:45:20 -08:00 |
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Jerry Zhao
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604cb6358f
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Bump fpga-platforms to new organized testchipip
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2023-12-19 12:33:37 -08:00 |
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-T.K.-
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ba7f3c21c8
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ADD: bump fpga-shell
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2023-12-17 23:22:49 -08:00 |
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Jerry Zhao
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30ac9dc2c8
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Merge remote-tracking branch 'origin/main' into tcip-bump
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2023-12-14 10:58:57 -08:00 |
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-T.K.-
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069a9d2999
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ADD: add equation for setting certain SPI clock speed
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2023-12-05 15:07:25 -08:00 |
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-T.K.-
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e78756704b
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FIX: fix vcu118 sd card frequency
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2023-12-04 18:14:50 -08:00 |
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-T.K.-
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e078fcba49
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REFACTOR: rename arty35t explicitly
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2023-12-04 01:54:59 -08:00 |
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Jerry ZhaoandGitHub
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6445233d8d
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Merge pull request #1657 from ucb-bar/artygpio
Add Bringup on Arty100T config, using PMOD-gpio for ser-tl
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2023-11-19 13:45:18 -08:00 |
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Jerry Zhao
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9dc0c8fe75
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Fix bringup config timing
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2023-11-17 14:42:26 -08:00 |
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Jerry Zhao
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ff668a98ac
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Fix cloneType not inferring direction for arty100t uart-tsi
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2023-11-17 14:37:07 -08:00 |
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Jerry Zhao
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1d6ebb230b
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Add Bringup on Arty100T config, using PMOD-gpio for ser-tl
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2023-11-08 20:06:44 -08:00 |
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Jerry Zhao
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6bb173bd21
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Fix vc707 clock freqs
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2023-10-31 21:40:45 -07:00 |
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Jerry Zhao
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a8766ea8fc
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Precisely specify bus frequencies
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2023-10-31 14:25:16 -07:00 |
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Jerry Zhao
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3fa3d745b9
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Support breaking out ChipTop I/O out of the expected bundle type
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2023-10-30 21:25:11 -07:00 |
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Jerry Zhao
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a5597fd32f
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Support using HarnessBinders without IOBinders
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2023-10-25 11:49:16 -07:00 |
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Jerry Zhao
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0ebab140ff
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Update nexysvideo to Port api
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2023-10-09 11:49:38 -07:00 |
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Jerry Zhao
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8ecd7bfa89
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Merge remote-tracking branch 'origin/main' into port_api
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2023-10-09 11:18:00 -07:00 |
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Jerry Zhao
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eb3a0aecf4
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Add PortAPI between IO and Harness blocks
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2023-10-05 15:02:56 -07:00 |
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Vladimir Milovanovićandpznikola
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3d96cf5bc9
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Adds initial Nexys Video board support.
Co-authored-by: pznikola <p.z.nikola@etf.rs>
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2023-10-05 23:01:29 +02:00 |
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Vladimir Milovanović
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7debb5f52d
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Bump fpga-shells.
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2023-10-06 09:54:42 +02:00 |
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Jerry ZhaoandGitHub
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adebd634b4
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Fix Arty100T Verilog build (#1608)
* Bump rocket-chip
* Bump fpga-shells
* Add Arty100T Verilog build to CI
* Fix Arty100T harness disconnected LEDs
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2023-09-27 13:03:37 +02:00 |
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Jerry ZhaoandGitHub
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0b81a82459
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Fix VCU118 freq adjustment configs
Resolves #1583
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2023-09-06 10:55:53 -07:00 |
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Jerry Zhao
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5495d05aa0
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Bump to latest rocket-chip
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2023-08-22 11:28:57 -07:00 |
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Jerry Zhao
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ef3409f87f
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Merge remote-tracking branch 'origin/main' into rcbump
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2023-07-09 23:31:16 -07:00 |
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Jerry Zhao
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078bce1323
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Bump to chisel3.6
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2023-07-05 10:32:55 -07:00 |
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Jerry Zhao
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89db2372c3
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Merge remote-tracking branch 'origin/main' into tetheredsim
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2023-05-31 21:55:09 -07:00 |
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Jerry ZhaoandGitHub
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ea127aa815
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Merge pull request #1475 from ucb-bar/bumprc
Bump to latest rocket-chip
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2023-05-30 21:59:00 -07:00 |
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jerryho
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9844deb172
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using dp(ExtTLMem).get.master.beatBytes to obtain MemoryBus data width
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2023-05-27 18:12:56 +08:00 |
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jerryho
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45eeee5092
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fix the data field width mismatch between AXI that goes to MIG core and that of the Memory Bus
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2023-05-26 16:08:59 +08:00 |
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Jerry Zhao
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889713b5b1
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Switch to UARTTSIIO
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2023-05-24 19:15:11 -07:00 |
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Jerry Zhao
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6a42c64d3a
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Bump to latest rocket-chip
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2023-05-24 10:17:37 -07:00 |
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Jerry Zhao
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57f5168408
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Set number of idbits correctly for fpga ddr
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2023-05-15 00:04:12 -07:00 |
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Jerry Zhao
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f4739be632
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Update multi-chip API for harnesses
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2023-05-15 00:03:22 -07:00 |
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Jerry Zhao
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2077e4304d
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Explicitly provide refClockFreqMHz to harnessClockInstantiator
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2023-05-13 11:18:03 -07:00 |
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Jerry Zhao
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b8e95e0305
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Rename implicit clock/reset to referenceclock/reset
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2023-05-12 15:11:44 -07:00 |
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Jerry Zhao
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607c2b5a73
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Unify multi-node btw chipyard/firechip | unify harness clocking
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2023-05-12 08:41:34 -07:00 |
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Jerry Zhao
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64ad77bbcf
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Make FPGA flows use the harnessClockInstantiator
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2023-05-11 15:04:04 -07:00 |
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Jerry Zhao
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eced8e63d9
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Rename SerialAdapter+SimSerial to TSIToTileLink/SimTSI/TSIHarness
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2023-05-08 18:19:18 -07:00 |
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Jerry Zhao
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ac281daa78
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Move TestHarness to chipyard.harness, make chipyard/harness directory
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2023-05-08 08:00:56 -07:00 |
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Jerry Zhao
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5f076b184d
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Flip serial_tl_clock to be generated off-chip
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2023-05-07 22:22:36 -07:00 |
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Jerry Zhao
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e93bc3bed7
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Fix Arty FPGA reset harness binder
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2023-04-01 13:53:56 -07:00 |
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