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ADD: add equation for setting certain SPI clock speed

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-T.K.-
2023-12-05 15:07:25 -08:00
parent e78756704b
commit 069a9d2999
1 changed files with 12 additions and 9 deletions
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21
fpga/src/main/resources/vcu118/sdboot/sd.c
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@@ -22,7 +22,14 @@
#error Must define TL_CLK
#endif
#define F_CLK (TL_CLK)
#define F_CLK (TL_CLK)
// SPI SCLK frequency, in kHz
#define SPI_CLK 1250
// SPI clock divisor value
// @see https://ucb-bar.gitbook.io/baremetal-ide/baremetal-ide/using-peripheral-devices/sifive-ips/serial-peripheral-interface-spi
#define SPI_DIV (((F_CLK * 1000) / SPI_CLK) / 2 - 1)
static volatile uint32_t * const spi = (void *)(SPI_CTRL_ADDR);
@@ -80,8 +87,8 @@ static void sd_poweron(void)
{
long i;
// HACK: frequency change
// REG32(spi, SPI_REG_SCKDIV) = (F_CLK / 300000UL);
REG32(spi, SPI_REG_SCKDIV) = (F_CLK * 2.5);
REG32(spi, SPI_REG_SCKDIV) = SPI_DIV;
REG32(spi, SPI_REG_CSMODE) = SPI_CSMODE_OFF;
for (i = 10; i > 0; i--) {
sd_dummy();
@@ -173,14 +180,10 @@ static int copy(void)
dputs("CMD18");
kprintf("LOADING 0x%xB PAYLOAD\r\n", PAYLOAD_SIZE_B);
kprintf("LOADING 0x%x B PAYLOAD\r\n", PAYLOAD_SIZE_B);
kprintf("LOADING ");
// TODO: Speed up SPI freq. (breaks between these two values)
//REG32(spi, SPI_REG_SCKDIV) = (F_CLK / 16666666UL);
// HACK: frequency change
// REG32(spi, SPI_REG_SCKDIV) = (F_CLK / 5000000UL);
REG32(spi, SPI_REG_SCKDIV) = (F_CLK * 2); // / 0.5
REG32(spi, SPI_REG_SCKDIV) = SPI_DIV;
if (sd_cmd(0x52, BBL_PARTITION_START_SECTOR, 0xE1) != 0x00) {
sd_cmd_end();
return 1;