wu-arch/chipyard
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165 Commits

Author SHA1 Message Date
Jerry Zhao
04e80a6984 Bump rocketchip to latest, chisel to 3.5.2 
Remove fork of BusTopologies from rocket-chip

Update generators/chipyard/src/main/scala/config/AbstractConfig.scala

Co-authored-by: Abraham Gonzalez <abe.j.gonza@gmail.com>
 2022-09-16 15:17:30 -07:00
Sagar Karandikar
8c56a5fe3c Merge pull request #1172 from ucb-bar/firesim-no-mem 
firesim: Add a config with no mem port
 2022-06-15 11:55:07 -07:00
David Biancolin
26dc18e878 firesim: Add a config with no mem port 2022-06-09 08:28:20 -07:00
David Biancolin
70f16cbb46 [firechip] Properly string interpolate exit failure in ScalaTestSuite (#1095) 2022-01-21 08:48:27 -08:00
Jerry Zhao
f8d83dddf5 Increase default SerialTL width to 32 (#1040) 2021-11-12 12:23:48 -08:00
Jerry Zhao
f668ffdb03 Switch PRCI to HarnessBinder/IOBinders 2021-09-29 11:39:52 -07:00
David Biancolin
580d311059 Use ResetPulseBridge + GlobalResetCondition; bump FireSim 2021-09-11 01:36:02 +00:00
alonamid
76b747dc84 Merge pull request #836 from ucb-bar/firesim-default-freqs 
Sane FireSim Default Target Freqs
 2021-06-08 14:33:57 -07:00
alonamid
610adfc3f7 address PR review comments 2021-06-03 22:23:17 -07:00
alonamid
f2b56072a1 remove crossings in single clock domain 2021-06-02 21:26:29 -07:00
alonamid
06b8cf84f9 update default firesim config freqs 2021-06-02 20:00:02 -07:00
alonamid
225cf9d29a update frequency config fragements 2021-06-01 16:40:31 -07:00
David Biancolin
15a30a73e9 [firechip] Memomize Clock RecordMap creation to fix supernode 2021-05-07 06:39:45 +00:00
alonamid
b99d6bb7ac multiclock config multiple 2021-03-29 00:01:13 -07:00
alonamid
c93cd255ab sane firesim default target freqs 2021-03-25 23:28:07 -07:00
abejgonzalez
09ef82cabf Update harnessClk/Rst naming to buildtop | Small docs cleanup 2021-03-22 13:11:12 -07:00
abejgonzalez
5ffad327db Bump testchipip 2021-03-21 15:34:01 -07:00
abejgonzalez
55263971bc Use async queue to connect serdesser + other components 2021-03-19 20:49:49 -07:00
abejgonzalez
1e42113926 Splitting up FireSim default frequencies into a separate config frag. 2021-03-19 17:33:39 -07:00
abejgonzalez
5301723404 Use def instead of var Option for ref frequency 2021-03-16 19:42:24 -07:00
abejgonzalez
6476c7e7f0 Small renaming/cleanup | Use LinkedHashMaps 2021-03-15 16:54:42 -07:00
Jerry Zhao
a013f0d561 Fix SerialTL HarnessRAM BridgeBinder 2021-03-15 15:09:29 -07:00
Jerry Zhao
8a78565c04 Update BridgeBinders with new HarnessRAM clocking 2021-03-15 12:45:40 -07:00
Abraham Gonzalez
e4ccfe1bb9 Renaming updates | Have FireSim clocks request frequency by default 2021-03-08 23:43:00 +00:00
Abraham Gonzalez
6ab8f8f8fc Update FireSim to support harness clocks | Small config renaming 2021-03-08 22:03:07 +00:00
Abraham Gonzalez
3d962180be Cleanup | Fix BlockDevice clocking issues 2021-03-03 19:44:55 +00:00
Abraham Gonzalez
c52fce79ae Fix FireChip compilation | Remove extra DefaultSerialTL in bridges 2021-03-03 07:25:49 +00:00
abejgonzalez
f850df7a9f General renaming / cleanup 2021-03-02 22:58:05 -08:00
Abraham Gonzalez
1d287bede5 Enlarge serial width | Bugfix loadmem disable | Add TracerV 2021-03-03 02:43:38 +00:00
Abraham Gonzalez
a3e22c78de First attempt at getting Offchip AXI port 2021-02-28 22:27:18 +00:00
alonamid
6dcd4f9afc WithFireSimFAME5 to allow non Rocket/BOOM build 2021-02-01 17:33:07 -08:00
Albert Magyar
f7a98f23bc Merge pull request #756 from ucb-bar/16-largeboom 
Add 16-core LargeBOOM config to firechip
 2021-01-13 15:36:51 -08:00
Albert Magyar
c481dc2ee8 Add 16-core LargeBOOM config to firechip 
* Fix Jerry's comment on accidentally mixing multiple BOOM configs
 2021-01-12 23:12:10 -08:00
David Biancolin
1bd51447fe [ci skip] Fix Typo in firechip/src/test/scala/ScalaTestSuite.scala 
Co-authored-by: Abraham Gonzalez <abe.j.gonza@gmail.com>
 2020-12-13 10:45:51 -05:00
David Biancolin
8f1e20936f Update FireSim CI. Push threading into test context 2020-12-12 13:41:32 -08:00
David Biancolin
ee436c9b3f [firechip] Fix a uart multiclock bug 2020-12-10 07:18:12 +00:00
David Biancolin
230bd81e0e [firechip] Update legacy firechip config 2020-11-09 09:26:30 -08:00
Abraham Gonzalez
5c5a4b51e3 Merge pull request #710 from ucb-bar/rename-ariane 
Rename Ariane to CVA6
 2020-11-06 14:53:54 -08:00
abejgonzalez
a2ebbee2ac Rename Ariane to CVA6 2020-11-04 15:42:30 -08:00
David Biancolin
f504b7a0f5 [clocking] Improve reference clock selection using a multiple-of-fastest strategy 2020-11-03 09:14:55 -08:00
Jerry Zhao
e0bf907a06 Merge remote-tracking branch 'origin/dev' into lazy-iobinders 2020-10-19 13:22:01 -07:00
Jerry Zhao
9927231bc4 Support lazy-iobinders 2020-10-17 22:47:50 -07:00
David Biancolin
1b94e7f10c Merge remote-tracking branch 'origin/dev' into diplomatic-clocks-mbus-crossing 2020-10-16 23:21:20 +00:00
Albert Magyar
84e0bf7338 Don't annotate cores with FAMEModelAnnotations 2020-10-15 12:25:39 -07:00
Alon Amid
2c935b4ad7 pull firesim mem model config into firesim tweaks 2020-10-15 17:07:51 +00:00
David Biancolin
9c8d2948af [firechip] Fix a broken config 2020-10-14 15:33:32 -07:00
David Biancolin
6aefb73ab5 Merge remote-tracking branch 'origin/dev' into diplomatic-clocks-mbus-crossing 2020-10-14 15:29:00 -07:00
David Biancolin
211c33f996 Address comments in #690 2020-10-14 14:42:45 -07:00
David Biancolin
986b5831c8 [clocking] Sketch out a topology that puts the MBUS is a separate domain 2020-10-09 07:23:17 -07:00
David Biancolin
392d5b0801 [clocking] Synchronize all output clocks from DividerOnly generator 2020-10-07 09:32:48 -07:00