wu-arch/chipyard
1
0
Fork 0
Code Issues Pull Requests Actions 1 Packages Projects Releases Wiki Activity

Fix cloneType not inferring direction for arty100t uart-tsi

Browse Source
This commit is contained in:
Jerry Zhao
2023-11-17 14:37:07 -08:00
parent 1d6ebb230b
commit ff668a98ac
1 changed files with 1 additions and 1 deletions
Download Patch File Download Diff File Expand all files Collapse all files

2
fpga/src/main/scala/arty100t/HarnessBinders.scala
View File

@@ -48,7 +48,7 @@ class WithArty100TDDRTL extends HarnessBinder({
class WithArty100TSerialTLToGPIO extends HarnessBinder({ class WithArty100TSerialTLToGPIO extends HarnessBinder({
case (th: HasHarnessInstantiators, port: SerialTLPort) => { case (th: HasHarnessInstantiators, port: SerialTLPort) => {
val artyTh = th.asInstanceOf[LazyRawModuleImp].wrapper.asInstanceOf[Arty100THarness] val artyTh = th.asInstanceOf[LazyRawModuleImp].wrapper.asInstanceOf[Arty100THarness]
val harnessIO = IO(port.io.cloneType).suggestName("serial_tl") val harnessIO = IO(chiselTypeOf(port.io)).suggestName("serial_tl")
harnessIO <> port.io harnessIO <> port.io
val clkIO = IOPin(harnessIO.clock) val clkIO = IOPin(harnessIO.clock)
val packagePinsWithPackageIOs = Seq( val packagePinsWithPackageIOs = Seq(