From ff668a98ac9b452e5fc018d213d4414843cbf5b5 Mon Sep 17 00:00:00 2001 From: Jerry Zhao Date: Fri, 17 Nov 2023 14:37:07 -0800 Subject: [PATCH] Fix cloneType not inferring direction for arty100t uart-tsi --- fpga/src/main/scala/arty100t/HarnessBinders.scala | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/fpga/src/main/scala/arty100t/HarnessBinders.scala b/fpga/src/main/scala/arty100t/HarnessBinders.scala index 1b1a95d5..4c821970 100644 --- a/fpga/src/main/scala/arty100t/HarnessBinders.scala +++ b/fpga/src/main/scala/arty100t/HarnessBinders.scala @@ -48,7 +48,7 @@ class WithArty100TDDRTL extends HarnessBinder({ class WithArty100TSerialTLToGPIO extends HarnessBinder({ case (th: HasHarnessInstantiators, port: SerialTLPort) => { val artyTh = th.asInstanceOf[LazyRawModuleImp].wrapper.asInstanceOf[Arty100THarness] - val harnessIO = IO(port.io.cloneType).suggestName("serial_tl") + val harnessIO = IO(chiselTypeOf(port.io)).suggestName("serial_tl") harnessIO <> port.io val clkIO = IOPin(harnessIO.clock) val packagePinsWithPackageIOs = Seq(