first attempt decoupling

generators/chipyard/src/main/scala/ConfigFragments.scala

@@ -3,7 +3,7 @@ package chipyard.config
 import chisel3._
 import chisel3.util.{log2Up}
 
-import freechips.rocketchip.config.{Field, Parameters, Config}
+import freechips.rocketchip.config.{Field, Parameters, Config, View}
 import freechips.rocketchip.subsystem.{SystemBusKey, RocketTilesKey, WithRoccExample, WithNMemoryChannels, WithNBigCores, WithRV32, CacheBlockBytes}
 import freechips.rocketchip.diplomacy.{LazyModule, ValName}
 import freechips.rocketchip.devices.tilelink.BootROMParams
@@ -13,7 +13,6 @@ import freechips.rocketchip.rocket.{RocketCoreParams, MulDivParams, DCacheParams
 import freechips.rocketchip.util.{AsyncResetReg}
 
 import boom.common.{BoomTilesKey}
-import ariane.{ArianeTilesKey}
 import testchipip._
 
 import hwacha.{Hwacha}
@@ -23,6 +22,7 @@ import sifive.blocks.devices.uart._
 import sifive.blocks.devices.spi._
 
 import chipyard.{BuildTop, BuildSystem}
+import chipyard.{CoreRegistrar, CoreRegisterEntryBase}
 
 /**
  * TODO: Why do we need this?
@@ -147,8 +147,21 @@ class WithControlCore extends Config((site, here, up) => {
   case MaxHartIdBits => log2Up(up(RocketTilesKey, site).size + up(BoomTilesKey, site).size + 1)
 })
 
+trait TraceIOMatch {
+  this: CoreRegisterEntryBase =>
+  val matchTile: (View, View, View) => PartialFunction[Field[Seq[TileParams]],Any] = ((site, here, up) => {
+    // TODO: XXX What's the "tile" here?
+    case tilesKey => up(tilesKey) map (tile => tile.copy(trace = true))
+  })
+}
+
 class WithTraceIO extends Config((site, here, up) => {
-  case BoomTilesKey => up(BoomTilesKey) map (tile => tile.copy(trace = true))
-  case ArianeTilesKey => up(ArianeTilesKey) map (tile => tile.copy(trace = true))
-  case TracePortKey => Some(TracePortParams())
+  val coreMatch = (coreList: List[CoreRegisterEntryBase]) => coreList match {
+    case coreEntry :: tail => coreEntry.matchTile(site, here, up) orElse coreMatch(tail)
+    case Nil => {
+      case BoomTilesKey => up(BoomTilesKey) map (tile => tile.copy(trace = true))
+      case TracePortKey => Some(TracePortParams())
+    }
+  }
+  coreMatch(CoreRegistrar.cores)
 })

generators/chipyard/src/main/scala/CoreRegistrar.scala

@@ -0,0 +1,37 @@
+package chipyard
+
+import chisel3._
+
+import freechips.rocketchip.config.{Parameters, Config, Field}
+import freechips.rocketchip.subsystem.{SystemBusKey, RocketTilesKey, RocketCrossingParams}
+import freechips.rocketchip.devices.tilelink.{BootROMParams}
+import freechips.rocketchip.diplomacy.{SynchronousCrossing, AsynchronousCrossing, RationalCrossing}
+import freechips.rocketchip.rocket._
+import freechips.rocketchip.tile._
+
+import ariane.{ArianeTile, ArianeTilesKey, ArianeCrossingKey, ArianeTileParams}
+
+import chipyard.config.TraceIOMatch
+
+// Third-party core entries
+sealed trait CoreRegisterEntryBase {
+  type Tile
+  type TitleParams
+  def tilesKey: Field[Seq[TitleParams]]
+  def crossingKey: Field[Seq[RocketCrossingParams]]
+}
+
+class CoreRegisterEntry[TileT <: BaseTile, TileParamsT <: CoreParams](tk: Field[Seq[TileParamsT]], ck: Field[Seq[RocketCrossingParams]]) 
+  extends CoreRegisterEntryBase with TraceIOMatch {
+  type Tile = TileT
+  type TileParams = TileParamsT
+  def tilesKey = tk
+  def crossingKey = ck
+}
+
+object CoreRegistrar {
+  val cores: List[CoreRegisterEntryBase] = List(
+    // ADD YOUR CORE DEFINITION HERE
+    new CoreRegisterEntry[ArianeTile, ArianeTileParams](ArianeTilesKey, ArianeCrossingKey)
+  )
+}

generators/chipyard/src/main/scala/Subsystem.scala

@@ -22,7 +22,6 @@ import freechips.rocketchip.subsystem._
 import freechips.rocketchip.amba.axi4._
 
 import boom.common.{BoomTile, BoomTilesKey, BoomCrossingKey, BoomTileParams}
-import ariane.{ArianeTile, ArianeTilesKey, ArianeCrossingKey, ArianeTileParams}
 
 import testchipip.{DromajoHelper}
 
@@ -36,14 +35,17 @@ trait HasChipyardTiles extends HasTiles
 
   protected val rocketTileParams = p(RocketTilesKey)
   protected val boomTileParams = p(BoomTilesKey)
-  protected val arianeTileParams = p(ArianeTilesKey)
+  protected val coreTileParams = CoreRegistrar.cores map (coreType => p(coreType.tilesKey))
 
   // crossing can either be per tile or global (aka only 1 crossing specified)
   private val rocketCrossings = perTileOrGlobalSetting(p(RocketCrossingKey), rocketTileParams.size)
   private val boomCrossings = perTileOrGlobalSetting(p(BoomCrossingKey), boomTileParams.size)
-  private val arianeCrossings = perTileOrGlobalSetting(p(ArianeCrossingKey), arianeTileParams.size)
+  private val coreCrossings = (CoreRegistrar.cores zip coreTileParams) map ((coreType, tileParams) =>
+    perTileOrGlobalSetting(p(coreType.crossingKey), tileParams.size))
 
-  val allTilesInfo = (rocketTileParams ++ boomTileParams ++ arianeTileParams) zip (rocketCrossings ++ boomCrossings ++ arianeCrossings)
+  // TODO: XXX The "tiles" below scan for hartId but it is not in CoreParams. Should that be added in later 
+  // revision, or I have to use reflection to get that parameter?
+  val allTilesInfo = (rocketTileParams ++ boomTileParams ++ coreTileParams) zip (rocketCrossings ++ boomCrossings ++ coreCrossings)
 
   // Make a tile and wire its nodes into the system,
   // according to the specified type of clock crossing.
@@ -55,17 +57,22 @@ trait HasChipyardTiles extends HasTiles
   val tiles = allTilesInfo.sortWith(_._1.hartId < _._1.hartId).map {
     case (param, crossing) => {
 
-      val tile = param match {
-        case r: RocketTileParams => {
-          LazyModule(new RocketTile(r, crossing, PriorityMuxHartIdFromSeq(rocketTileParams), logicalTreeNode))
-        }
-        case b: BoomTileParams => {
-          LazyModule(new BoomTile(b, crossing, PriorityMuxHartIdFromSeq(boomTileParams), logicalTreeNode))
-        }
-        case a: ArianeTileParams => {
-          LazyModule(new ArianeTile(a, crossing, PriorityMuxHartIdFromSeq(arianeTileParams), logicalTreeNode))
+      val tileMatch = coreAndtileParamsList => {
+        case (coreType, tileParams) :: tail => (param => {
+          case a: coreType.TileParams => {
+            LazyModule(new coreType.Tile(a, crossing, PriorityMuxHartIdFromSeq(tileParams), logicalTreeNode))
+          }
+        }) orElse tileMatch(tail)
+        case Nil => param => {
+          case r: RocketTileParams => {
+            LazyModule(new RocketTile(r, crossing, PriorityMuxHartIdFromSeq(rocketTileParams), logicalTreeNode))
+          }
+          case b: BoomTileParams => {
+            LazyModule(new BoomTile(b, crossing, PriorityMuxHartIdFromSeq(boomTileParams), logicalTreeNode))
+          }
         }
       }
+      val tile = tileMatch(CoreRegistrar.cores zip coreTileParams)
       connectMasterPortsToSBus(tile, crossing)
       connectSlavePortsToCBus(tile, crossing)
       connectInterrupts(tile, debugOpt, clintOpt, plicOpt)

generators/chipyard/src/main/scala/TestSuites.scala

@@ -3,12 +3,11 @@ package chipyard
 import scala.collection.mutable.{LinkedHashSet}
 
 import freechips.rocketchip.subsystem.{RocketTilesKey}
-import freechips.rocketchip.tile.{XLen}
-import freechips.rocketchip.config.{Parameters}
+import freechips.rocketchip.tile.{XLen, CoreParams}
+import freechips.rocketchip.config.{Parameters, Field}
 import freechips.rocketchip.system.{TestGeneration, RegressionTestSuite, RocketTestSuite}
 
 import boom.common.{BoomTilesKey}
-import ariane.{ArianeTilesKey}
 
 /**
  * A set of pre-chosen regression tests
@@ -144,11 +143,11 @@ class TestSuiteHelper
   }
 
   /**
-  * Add Ariane tests (asm, bmark, regression)
+  * Add third-party core (including Ariane) tests (asm, bmark, regression)
   */
-  def addArianeTestSuites(implicit p: Parameters) = {
+  def addThirdPartyTestSuites[TileParams <: CoreParams](tilesKey: Field[Seq[TileParams]])(implicit p: Parameters) = {
     val xlen = p(XLen)
-    p(ArianeTilesKey).find(_.hartId == 0).map { tileParams =>
+    p(tilesKey).find(_.hartId == 0).map { tileParams =>
       val coreParams = tileParams.core
       val vm = coreParams.useVM
       val env = if (vm) List("p","v") else List("p")

generators/chipyard/src/main/scala/stage/phases/AddDefaultTests.scala

@@ -17,7 +17,7 @@ import freechips.rocketchip.stage.phases.{RocketTestSuiteAnnotation}
 import freechips.rocketchip.system.{RocketTestSuite, TestGeneration}
 import freechips.rocketchip.util.HasRocketChipStageUtils
 
-import chipyard.TestSuiteHelper
+import chipyard.{TestSuiteHelper, CoreRegistrar}
 
 class AddDefaultTests extends Phase with PreservesAll[Phase] with HasRocketChipStageUtils {
   // Make sure we run both after RocketChip's version of this phase, and Rocket Chip's annotation emission phase
@@ -32,7 +32,7 @@ class AddDefaultTests extends Phase with PreservesAll[Phase] with HasRocketChipS
     val suiteHelper = new TestSuiteHelper
     suiteHelper.addRocketTestSuites
     suiteHelper.addBoomTestSuites
-    suiteHelper.addArianeTestSuites
+    CoreRegistrar.cores map suiteHelper.addThirdPartyTestSuites(_.tilesKey)
 
     // if hwacha parameter exists then generate its tests
     // TODO: find a more elegant way to do this. either through